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Add support for assume property (#2531)

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Peter Monsson 2020-09-03 18:38:48 +02:00 committed by GitHub
parent 80f5738544
commit 627d83e807
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3 changed files with 7 additions and 0 deletions
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@ -25,6 +25,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix queues as class members (#2525). [nanduraj1]
**** Add support for assume property. [Peter Monsson]
* Verilator 4.040 2020-08-15

1
src/verilog.y
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@ -5056,6 +5056,7 @@ concurrent_assertion_statement<nodep>: // ==IEEE: concurrent_assertion_statement
yASSERT yPROPERTY '(' property_spec ')' elseStmtBlock { $$ = new AstAssert($1, $4, nullptr, $6, false); }
//UNSUP yASSERT yPROPERTY '(' property_spec ')' action_block { }
// // IEEE: assume_property_statement
| yASSUME yPROPERTY '(' property_spec ')' elseStmtBlock { $$ = new AstAssert($1, $4, nullptr, $6, false); }
//UNSUP yASSUME yPROPERTY '(' property_spec ')' action_block { }
// // IEEE: cover_property_statement
| yCOVER yPROPERTY '(' property_spec ')' stmtBlock { $$ = new AstCover($1, $4, $6, false); }

4
test_regress/t/t_assert_property.v
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@ -38,13 +38,17 @@ module Test
`ifdef FAIL_ASSERT_1
assert property (@(posedge clk) cyc==3)
else $display("cyc != 3, cyc == %0d", cyc);
assume property (@(posedge clk) cyc==3)
else $display("cyc != 3, cyc == %0d", cyc);
`endif
`ifdef FAIL_ASSERT_2
assert property (@(posedge clk) cyc!=3);
assume property (@(posedge clk) cyc!=3);
`endif
assert property (@(posedge clk) cyc < 100);
assume property (@(posedge clk) cyc < 100);
restrict property (@(posedge clk) cyc==1); // Ignored in simulators