Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

De-tabify

Browse Source
This commit is contained in:
Todd Strader 2020-02-24 05:34:10 -05:00
parent f7d1c6ca72
commit 60f82961b4
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
test_regress/t/t_prot_lib.v
View File

@ -15,14 +15,14 @@ if (cyc > 0 && sig``_in != sig``_out) begin \
end
module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
localparam last_cyc =
`ifdef TEST_BENCHMARK
`TEST_BENCHMARK;
`TEST_BENCHMARK;
`else
10;
`endif