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Fix parameters not supported in constant functions, bug474.

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This commit is contained in:
Wilson Snyder 2012-05-03 21:59:47 -04:00
parent b9101c3d6a
commit 5fc98cce0d
4 changed files with 63 additions and 2 deletions
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2
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@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Fix generate operators not short circuiting, bug413. [by Jeremy Bennett]
*** Fix parameters not supported in constant functions, bug474. [Alex Solomatnikov]
**** Fix ITOD internal error on real conversions, bug491. [Alex Solomatnikov]
**** Fix input and real loosing real data type, bug501. [Alex Solomatnikov]

12
src/V3Simulate.h
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@ -102,7 +102,7 @@ private:
// Checking METHODS
public:
/// Call other-this function on all new var references
/// Call other-this function on all new *non-constant* var references
virtual void varRefCb(AstVarRef* nodep) {}
void clearOptimizable(AstNode* nodep/*null ok*/, const string& why) {
@ -272,7 +272,15 @@ private:
if (!(vscp->user1() & VU_RV)) {
if (!m_params && (vscp->user1() & VU_LV)) clearOptimizable(nodep,"Var write & read");
vscp->user1( vscp->user1() | VU_RV);
if (m_checkOnly) varRefCb (nodep);
bool isConst = nodep->varp()->isParam();
AstConst* constp = (isConst ? nodep->varp()->valuep()->castConst() : NULL);
if (isConst && constp) { // Propagate PARAM constants for constant function analysis
if (!m_checkOnly && optimizable()) {
newNumber(vscp)->opAssign(constp->num());
}
} else {
if (m_checkOnly) varRefCb (nodep);
}
}
}
if (!m_checkOnly && optimizable()) { // simulating

18
test_regress/t/t_param_while.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

33
test_regress/t/t_param_while.v Normal file
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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
//bug505
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter WIDTH = 33;
localparam MAX_WIDTH = 11;
localparam NUM_OUT = num_out(WIDTH);
wire [NUM_OUT-1:0] z;
function integer num_out;
input integer width;
num_out = 1;
while ((width + num_out - 1) / num_out > MAX_WIDTH)
num_out = num_out * 2;
endfunction
initial begin
if (NUM_OUT != 4) $stop;
if ($bits(z) != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule