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Fix passing parameter type instantiations by position number.

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This commit is contained in:
Wilson Snyder 2020-12-05 10:59:33 -05:00
parent 7f6d4ac359
commit 5fb834e41e
4 changed files with 26 additions and 11 deletions
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2
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@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 4.107 devel
**** Fix passing parameter type instantiations by position number.
* Verilator 4.106 2020-12-02

8
src/V3LinkDot.cpp
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@ -1161,7 +1161,7 @@ class LinkDotFindVisitor final : public AstNVisitor {
VSymEnt* insp
= m_statep->insertSym(m_curSymp, nodep->name(), nodep, m_classOrPackagep);
if (m_statep->forPrimary() && nodep->isGParam()) {
m_paramNum++;
++m_paramNum;
VSymEnt* symp
= m_statep->insertSym(m_curSymp, "__paramNumber" + cvtToStr(m_paramNum),
nodep, m_classOrPackagep);
@ -1191,6 +1191,12 @@ class LinkDotFindVisitor final : public AstNVisitor {
UASSERT_OBJ(m_curSymp, nodep, "Parameter type not under module/package/$unit");
iterateChildren(nodep);
m_statep->insertSym(m_curSymp, nodep->name(), nodep, m_classOrPackagep);
if (m_statep->forPrimary() && nodep->isGParam()) {
++m_paramNum;
VSymEnt* symp = m_statep->insertSym(m_curSymp, "__paramNumber" + cvtToStr(m_paramNum),
nodep, m_classOrPackagep);
symp->exported(false);
}
}
virtual void visit(AstCFunc* nodep) override {
// For dotted resolution, ignore all AstVars under functions, otherwise shouldn't exist

3
test_regress/t/t_class_vparam.out
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@ -1,7 +1,4 @@
%Error-UNSUPPORTED: t/t_class_vparam.v:13:40: Unsupported: parameterized packages
13 | pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
| ^~~~~~~~~~~~~~~
%Error: t/t_class_vparam.v:13:58: Parameter pin not found: '__paramNumber1'
13 | pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
| ^~~~~~~
%Error: Exiting due to

24
test_regress/t/t_param_type3.v
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@ -17,32 +17,42 @@ module t (/*AUTOARG*/
output T_t o;
output T_t o2;
sub #(.T_t(T_t))
sub (.i, .o);
sub1 #(.T_t(T_t), .CHECK(1))
sub1 (.i, .o);
sub2 #(.T_t(T_t))
sub2 #(.T_t(T_t), .CHECK(2))
sub2 (.i, .o(o2));
sub1 #(T_t, 1)
sub1b (i, o);
sub2 #(T_t, 2)
sub2b (i, o2);
endmodule
module sub (i,o);
parameter type T_t = logic;
module sub1 (i,o);
parameter type T_t = real;
localparam type T2_t = T_t;
parameter int CHECK = 0;
input T_t i;
output T2_t o;
assign o = i;
if (CHECK != 1) $error;
endmodule
module sub2
#(
parameter type T_t = logic,
localparam type T2_t = T_t
parameter type T_t = real,
localparam type T2_t = T_t,
parameter int CHECK = 0
)
(
input T_t i,
output T_t o
);
assign o = i;
if (CHECK != 2) $error;
endmodule
// Local Variables: