forked from github/verilator
Fix test
This commit is contained in:
Wilson Snyder
parent
e931c6230a
commit
5eded789aa
@ -1,142 +1,261 @@
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module Vt_debug_emitv___024root;
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module Vt_debug_emitv_t;
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input logic clk;
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input logic in;
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signed int [31:0] t.array[0:2];
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logic [15:0] t.pubflat;
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logic [15:0] t.pubflat_r;
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signed int [31:0] t.fd;
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signed int [31:0] t.i;
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signed int [31:0] t.cyc;
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signed int [31:0] t.fo;
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signed int [31:0] t.sum;
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signed real t.r;
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string t.str;
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signed int [31:0] t._Vpast_0_0;
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signed int [31:0] t._Vpast_1_0;
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signed int [31:0] t.unnamedblk3.i;
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@(*)@([settle])@([initial])@(posedge clk)@(negedge
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clk)always @(
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*)@(
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[settle])@(
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[initial])@(
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posedge
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clk)@(
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negedge
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clk) begin
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$display("stmt");
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end
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always @([settle])@([initial])@(posedge clk)@(negedge
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clk) begin
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$display("stmt");
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end
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initial begin
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// Function: f
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$write("stmt\nstmt 0 99\n");
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// Function: t
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$display("stmt");
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// Function: f
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$write("stmt\nstmt 1 -1\n");
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// Function: t
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$display("stmt");
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// Function: f
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$display("stmt");
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$display("stmt 2 -2");
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// Function: t
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$display("stmt");
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$display("stmt");
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end
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typedef
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???? // ENUMDTYPE 't.e_t'
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???? // CFUNC '_final_TOP'
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???? // ENUMITEM 'ZERO'
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32'h0
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???? // ENUMITEM 'ONE'
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'sh1
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???? // REFDTYPE 'e_t'
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struct packed
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{
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???? // REFDTYPE 'e_t'
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a}signed logic [2:0] struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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signed int [31:0]
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???? // UNSIZEDARRAYDTYPE
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] e_t;
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typedef struct packed
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{
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???? // REFDTYPE 'e_t'
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a}signed logic [2:0] struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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signed int [31:0]
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???? // UNSIZEDARRAYDTYPE
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] ps_t;
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typedef struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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signed int [31:0]
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???? // UNSIZEDARRAYDTYPE
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] us_t;
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typedef union
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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signed int [31:0]
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???? // UNSIZEDARRAYDTYPE
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] union_t;
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struct packed
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{
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???? // REFDTYPE 'e_t'
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a} ps[0:2];
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struct
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{signed logic [2:0] a} us;
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union
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{logic a} unu;
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signed int [31:0] array[0:2];
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initial begin
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array = '{0:32'sh1, 1:32'sh2, 2:32'sh3};
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end
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logic [15:0] pubflat;
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logic [15:0] pubflat_r;
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logic [15:0] pubflat_w;
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assign pubflat_w = pubflat;
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signed int [31:0] fd;
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signed int [31:0] i;
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???? // QUEUEDTYPE
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q;
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???? // ASSOCARRAYDTYPE
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assoc;
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???? // DYNARRAYDTYPE
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dyn;
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task t;
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$display("stmt");
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always @(posedge clk)@(negedge clk) begin
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endtask
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function f;
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input signed int [31:0] v;
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begin : label0
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$display("stmt");
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f = ((v == 'sh0) ? 'sh63 : ((~ v) + 'sh1));
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disable label0;
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end
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endfunction
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initial begin
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begin : unnamedblk1
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signed int [31:0] other;
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begin
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begin : unnamedblk2
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signed int [31:0] i;
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i = 'sh0;
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while ((i < 'sh3)) begin
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begin
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other = f(i);
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$display("stmt %~ %~",
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iother, other);
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t()end
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i = (i + 'h1);
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end
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end
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end
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begin : named
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$display("stmt");
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end
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end
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end
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final begin
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begin
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$display("stmt");
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end
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end
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always @([any] in) begin
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begin
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$display("stmt");
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end
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end
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always @(posedge clk) begin
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begin
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$display("posedge clk");
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end
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t.pubflat_r <= t.pubflat;
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end
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t.cyc <= (32'sh1 + t.cyc);
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__Vdly__t.r <= (0.01 + t.r);
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t.fo = t.cyc;
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// Function: inc
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__Vtask_t.sub.inc__2__i = t.fo;
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__Vtask_t.sub.inc__2__o = (32'h1 + __Vtask_t.sub.inc__2__i[31:1]);
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t.sum = __Vtask_t.sub.inc__2__o;
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// Function: f
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__Vfunc_t.sub.f__3__v = t.sum;
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begin : label0
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begin : label0
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if ((32'sh0 == __Vfunc_t.sub.f__3__v)) begin
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__Vfunc_t.sub.f__3__Vfuncout = 32'sh21;
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disable label0;
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end
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__Vfunc_t.sub.f__3__Vfuncout = (32'h1
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+ __Vfunc_t.sub.f__3__v[2]);
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disable label0;
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pubflat_r <= pubflat_w;
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end
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end
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t.sum = __Vfunc_t.sub.f__3__Vfuncout;
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$display("[%0t] sum = %~", $timet.sum, t.sum);
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$display("a?= %d", ($c(32'sh1) ? $c(32'sh14)
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: $c(32'sh1e)));
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always @(negedge clk) begin
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begin
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$display("negedge clk, pfr = %x", pubflat_r);
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end
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end
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signed int [31:0] cyc;
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signed int [31:0] fo;
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signed int [31:0] sum;
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signed real r;
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string str;
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always @(posedge clk) begin
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begin
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cyc <= (cyc + 'sh1);
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r <= (r + 0.01);
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fo = cyc;
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sub.inc(fosum)sum = sub.f(sum);
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$display("[%0t] sum = %~", $timesum, sum);
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$display("a?= %d", ($c('sh1) ? $c('sh14)
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: $c('sh1e)));
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$c(;);
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$display("%d", $c(0));
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$fopen(72'h2f6465762f6e756c6c);
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$fclose(t.fd);
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$fclose(fd);
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$fopen(72'h2f6465762f6e756c6c, 8'h72);
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$fgetc(t.fd);
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$fflush(t.fd);
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$fscanf(t.fd, "%d", t.sum);
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$fgetc(fd);
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$fflush(fd);
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$fscanf(fd, "%d", sum);
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;
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$fdisplay(32'h69203d20, "%~", t.sum);
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$fwrite(t.fd, "hello");
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$readmemh(t.fd, t.array);
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$readmemh(t.fd, t.array, 32'sh0);
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$readmemh(t.fd, t.array, 32'sh0, 32'sh0);
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t.sum = 32'sh0;
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t.unnamedblk3.i = 32'sh0;
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$fdisplay(32'h69203d20, "%~", sum);
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$fwrite(fd, "hello");
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$readmemh(fd, array);
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$readmemh(fd, array, 'sh0);
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$readmemh(fd, array, 'sh0, 'sh0);
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sum = 'sh0;
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begin : unnamedblk3
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signed int [31:0] i;
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i = 'sh0;
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begin : label0
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while ((t.unnamedblk3.i < t.cyc)) begin
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t.sum = (t.sum + t.unnamedblk3.i);
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if ((32'sha < t.sum)) begin
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while ((i < cyc)) begin
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begin
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sum = (sum + i);
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if ((sum > 'sha)) begin
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disable label0;
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end
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else begin
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t.sum = (32'sh1 + t.sum);
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end
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t.unnamedblk3.i = (32'h1 + t.unnamedblk3.i);
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sum = (sum + 'sh1);
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end
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end
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if ((32'sh63 == t.cyc)) begin
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i = (i + 'h1);
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end
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end
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end
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if ((cyc == 'sh63)) begin
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$finish;
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end
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if ((32'sh64 == t.cyc)) begin
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if ((cyc == 'sh64)) begin
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$stop;
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end
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if (in) begin
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$display("1");
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case (in)
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'sh1: begin $display("1");
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end
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else begin
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$display("default");
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default: begin $display("default");
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end
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if (in) begin
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$display("1");
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endcase
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priority case (in)
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'sh1: begin $display("1");
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end
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else begin
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$display("default");
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default: begin $display("default");
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end
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if (in) begin
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$display("1");
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endcase
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unique case (in)
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'sh1: begin $display("1");
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end
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else begin
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$display("default");
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default: begin $display("default");
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end
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if (in) begin
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$display("1");
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endcase
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unique0 case (in)
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'sh1: begin $display("1");
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end
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else begin
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$display("default");
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default: begin $display("default");
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end
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endcase
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if (in) begin
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$display("1");
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end
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@ -161,86 +280,89 @@ module Vt_debug_emitv___024root;
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else begin
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$display("0");
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end
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$display("%~%~", t._Vpast_0_0t._Vpast_1_0,
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t._Vpast_1_0);
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t.str = $sformatf("cyc=%~", t.cyc);
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$display("%~%~", $past(cyc)$past(cyc, 'sh1),
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$past(cyc, 'sh1));
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str = $sformatf("cyc=%~", cyc);
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;
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$display("str = %@", t.str);
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$display("%% [%t] [%^] to=%o td=%d", $time$realtime
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$time$time, $realtime$time$time, $time
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$time, $time);
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$sscanf(40'h666f6f3d35, "foo=%d", t.i);
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$display("str = %@", str);
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$display("%% [%t] [%^] to=%o td=%d", $time
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$realtime$time$time, $realtime
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$time$time, $time$time, $time);
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$sscanf(40'h666f6f3d35, "foo=%d", i);
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;
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$printtimescale;
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if ((32'sh5 != t.i)) begin
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if ((i != 'sh5)) begin
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$stop;
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end
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t.sum =
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sum =
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???? // RAND
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32'sha;
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$display("%g", $log10(t.r));
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$display("%g", $ln(t.r));
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$display("%g", $exp(t.r));
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$display("%g", $sqrt(t.r));
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$display("%g", $floor(t.r));
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$display("%g", $ceil(t.r));
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$display("%g", $sin(t.r));
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$display("%g", $cos(t.r));
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$display("%g", $tan(t.r));
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$display("%g", $asin(t.r));
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$display("%g", $acos(t.r));
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$display("%g", $atan(t.r));
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$display("%g", $sinh(t.r));
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$display("%g", $cosh(t.r));
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$display("%g", $tanh(t.r));
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$display("%g", $asinh(t.r));
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$display("%g", $acosh(t.r));
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$display("%g", $atanh(t.r));
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;
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sum =
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???? // RAND
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'sha;
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sum =
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???? // RAND
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;
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sum =
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???? // RAND
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'sha;
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if ((PKG_PARAM != 'sh1)) begin
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$stop;
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end
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/*verilator public_flat_rw @(posedge clk)@(negedge
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clk) t.pubflat*/
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always @(posedge clk)@(negedge clk) begin
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__Vdly__t._Vpast_0_0 <= t.cyc;
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sub.r = 62;
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$display("%g", $log10(r));
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$display("%g", $ln(r));
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$display("%g", $exp(r));
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$display("%g", $sqrt(r));
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$display("%g", $floor(r));
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$display("%g", $ceil(r));
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$display("%g", $sin(r));
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$display("%g", $cos(r));
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$display("%g", $tan(r));
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$display("%g", $asin(r));
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$display("%g", $acos(r));
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$display("%g", $atan(r));
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$display("%g", $sinh(r));
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$display("%g", $cosh(r));
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$display("%g", $tanh(r));
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$display("%g", $asinh(r));
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$display("%g", $acosh(r));
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$display("%g", $atanh(r));
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end
|
||||
always @(posedge clk)@(negedge clk) begin
|
||||
__Vdly__t._Vpast_1_0 <= t.cyc;
|
||||
end
|
||||
__Vdly__t._Vpast_1_0 = t._Vpast_1_0;
|
||||
t._Vpast_1_0 = __Vdly__t._Vpast_1_0;
|
||||
__Vdly__t._Vpast_0_0 = t._Vpast_0_0;
|
||||
t._Vpast_0_0 = __Vdly__t._Vpast_0_0;
|
||||
__Vdly__t.r = t.r;
|
||||
t.r = __Vdly__t.r;
|
||||
__Vdly__t.cyc = t.cyc;
|
||||
t.cyc = __Vdly__t.cyc;
|
||||
__Vdly__t.pubflat_r = t.pubflat_r;
|
||||
t.pubflat_r = __Vdly__t.pubflat_r;
|
||||
always @(negedge clk) begin
|
||||
$display("negedge clk, pfr = %x", t.pubflat_r);
|
||||
end
|
||||
signed int [31:0] __Vtask_t.sub.inc__2__i;
|
||||
signed int [31:0] __Vtask_t.sub.inc__2__o;
|
||||
signed int [31:0] __Vfunc_t.sub.f__3__Vfuncout;
|
||||
signed int [31:0] __Vfunc_t.sub.f__3__v;
|
||||
logic [15:0] __Vdly__t.pubflat_r;
|
||||
signed int [31:0] __Vdly__t.cyc;
|
||||
signed real __Vdly__t.r;
|
||||
signed int [31:0] __Vdly__t._Vpast_0_0;
|
||||
signed int [31:0] __Vdly__t._Vpast_1_0;
|
||||
/*verilator public_flat_rw @(posedge clk) pubflat*/
|
||||
endmodule
|
||||
package Vt_debug_emitv___024unit;
|
||||
endpackage
|
||||
package Vt_debug_emitv_Pkg;
|
||||
endpackage
|
||||
class Vt_debug_emitv___024unit__03a__03aCls;
|
||||
class Vt_debug_emitv_Cls;
|
||||
signed int [31:0] member;
|
||||
|
||||
???? // CFUNC '__VnoInFunc_method'
|
||||
|
||||
???? // CFUNC 'new'
|
||||
$_CSTMT(_ctor_var_reset(vlSymsp);
|
||||
);
|
||||
$unit::Cls.member = 32'sh1;
|
||||
member = 'sh1;
|
||||
task method;
|
||||
endtask
|
||||
task new;
|
||||
endtask
|
||||
endclass
|
||||
/*class*/package Vt_debug_emitv___024unit__03a__03aCls__Vclpkg;
|
||||
end/*class*/package
|
||||
endpackage
|
||||
module Vt_debug_emitv_sub;
|
||||
task inc;
|
||||
input signed int [31:0] i;
|
||||
output signed int [31:0] o;
|
||||
o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1);
|
||||
endtask
|
||||
function f;
|
||||
input signed int [31:0] v;
|
||||
begin : label0
|
||||
begin : label0
|
||||
if ((v == 'sh0)) begin
|
||||
f = 'sh21;
|
||||
disable label0;
|
||||
end
|
||||
f = ({32'h1{{31'h0, v[2]}}} + 32'h1);
|
||||
disable label0;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
signed real r;
|
||||
endmodule
|
||||
package Vt_debug_emitv_Pkg;
|
||||
signed logic [31:0] PKG_PARAM;
|
||||
endpackage
|
||||
|
||||
@ -16,7 +16,7 @@ lint(
|
||||
v_flags => ["--lint-only --dump-treei 9 --dump-treei-V3EmitV 9 --debug-emitv"],
|
||||
);
|
||||
|
||||
files_identical("$Self->{obj_dir}/$Self->{VM_PREFIX}__preorder.v", $Self->{golden_filename});
|
||||
files_identical(glob_one("$Self->{obj_dir}/$Self->{VM_PREFIX}_*_width.tree.v"), $Self->{golden_filename});
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user