forked from github/verilator
Repair of last 2 checkins; dots in wrong place when 2 level deep inline
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288d7bd9dc
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@ -217,7 +217,7 @@ public:
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puts(", \""); puts(nodep->fileline()->filename()); puts("\"");
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puts(", "); puts(cvtToStr(nodep->fileline()->lineno()));
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puts(", "); puts(cvtToStr(nodep->column()));
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puts(", \""); puts(nodep->hier()); puts("\"");
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puts(", \""); puts((nodep->hier()!=""?".":"")+nodep->hier()); puts("\"");
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puts(", \""); puts(nodep->typeText()); puts("\"");
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puts(", \""); puts(nodep->comment()); puts("\"");
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puts(");\n");
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@ -249,7 +249,9 @@ private:
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virtual void visit(AstCoverDecl* nodep, AstNUser*) {
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// Fix path in coverage statements
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if (m_cellp) {
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nodep->hier(m_cellp->prettyName()+"."+nodep->hier());
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nodep->hier(m_cellp->prettyName()
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+ (nodep->hier()!="" ? ".":"")
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+ nodep->hier());
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}
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nodep->iterateChildren(*this);
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}
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@ -16,6 +16,8 @@ module t_clk_two (/*AUTOARG*/
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// verilator lint_on GENCLK
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reg [31:0] count;
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t_clk_twob tb (.*);
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wire reset_h = ~reset_l;
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always @ (posedge fastclk) begin
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if (reset_h) clk2 <= 0;
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@ -26,3 +28,17 @@ module t_clk_two (/*AUTOARG*/
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else count <= count + 1;
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end
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endmodule
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module t_clk_twob (/*AUTOARG*/
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// Inputs
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fastclk, reset_l
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);
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input fastclk;
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input reset_l;
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always @ (posedge fastclk) begin
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// Extra line coverage point, just to make sure coverage
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// hierarchy under inlining lands properly
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if (reset_l) ;
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end
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endmodule
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