forked from github/verilator
Fix assertions with unique case inside, #2199.
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4
Changes
4
Changes
@ -19,6 +19,10 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc]
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**** Fix MinW portability, #2114. [Sean Cross]
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**** Fix assertions with unique case inside, #2199. [hdzhangdoc]
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* Verilator 4.030 2020-03-08
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@ -254,12 +254,15 @@ private:
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// Not parallel, but harmlessly so.
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} else {
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AstNode* propp = NULL;
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for (AstCaseItem* itemp = nodep->itemsp();
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itemp; itemp=VN_CAST(itemp->nextp(), CaseItem)) {
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for (AstNode* icondp = itemp->condsp();
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icondp!=NULL; icondp=icondp->nextp()) {
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for (AstCaseItem* itemp = nodep->itemsp(); itemp;
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itemp = VN_CAST(itemp->nextp(), CaseItem)) {
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for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) {
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AstNode* onep;
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if (nodep->casex() || nodep->casez() || nodep->caseInside()) {
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if (AstInsideRange* rcondp = VN_CAST(icondp, InsideRange)) {
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onep = rcondp->newAndFromInside(nodep->exprp(),
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rcondp->lhsp()->cloneTree(true),
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rcondp->rhsp()->cloneTree(true));
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} else if (nodep->casex() || nodep->casez() || nodep->caseInside()) {
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onep = AstEqWild::newTyped(itemp->fileline(),
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nodep->exprp()->cloneTree(false),
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icondp->cloneTree(false));
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21
test_regress/t/t_assert_inside_cond.pl
Executable file
21
test_regress/t/t_assert_inside_cond.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"],
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);
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execute(
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);
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ok(1);
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1;
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46
test_regress/t/t_assert_inside_cond.v
Normal file
46
test_regress/t/t_assert_inside_cond.v
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@ -0,0 +1,46 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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hit,
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// Inputs
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clk
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);
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input clk;
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output logic hit;
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logic [31:0] addr;
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int cyc;
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initial addr = 32'h380;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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`ifdef T_ASSERT_INSIDE_COND
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addr <= 32'h380;
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`elsif T_ASSERT_INSIDE_COND_BAD
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addr <= 32'h389;
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`else
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`error "Bad test define"
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`endif
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_comb begin
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hit = 0;
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unique case (addr[11:0]) inside
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[12'h380 : 12'h388]: begin
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hit = 1;
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end
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endcase
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end
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endmodule
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3
test_regress/t/t_assert_inside_cond_bad.out
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3
test_regress/t/t_assert_inside_cond_bad.out
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@ -0,0 +1,3 @@
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[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
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%Error: t/t_assert_inside_cond.v:39: Verilog $stop
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Aborting...
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25
test_regress/t/t_assert_inside_cond_bad.pl
Executable file
25
test_regress/t/t_assert_inside_cond_bad.pl
Executable file
@ -0,0 +1,25 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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top_filename("t/t_assert_inside_cond.v");
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compile(
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verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"],
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);
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execute(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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