Fix assertions with unique case inside, #2199.

This commit is contained in:
Wilson Snyder 2020-03-30 18:13:51 -04:00
parent 0cf44a9c4f
commit 5c72f01598
6 changed files with 107 additions and 5 deletions

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@ -19,6 +19,10 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc]
**** Fix MinW portability, #2114. [Sean Cross]
**** Fix assertions with unique case inside, #2199. [hdzhangdoc]
* Verilator 4.030 2020-03-08

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@ -254,12 +254,15 @@ private:
// Not parallel, but harmlessly so.
} else {
AstNode* propp = NULL;
for (AstCaseItem* itemp = nodep->itemsp();
itemp; itemp=VN_CAST(itemp->nextp(), CaseItem)) {
for (AstNode* icondp = itemp->condsp();
icondp!=NULL; icondp=icondp->nextp()) {
for (AstCaseItem* itemp = nodep->itemsp(); itemp;
itemp = VN_CAST(itemp->nextp(), CaseItem)) {
for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) {
AstNode* onep;
if (nodep->casex() || nodep->casez() || nodep->caseInside()) {
if (AstInsideRange* rcondp = VN_CAST(icondp, InsideRange)) {
onep = rcondp->newAndFromInside(nodep->exprp(),
rcondp->lhsp()->cloneTree(true),
rcondp->rhsp()->cloneTree(true));
} else if (nodep->casex() || nodep->casez() || nodep->caseInside()) {
onep = AstEqWild::newTyped(itemp->fileline(),
nodep->exprp()->cloneTree(false),
icondp->cloneTree(false));

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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"],
);
execute(
);
ok(1);
1;

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@ -0,0 +1,46 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
hit,
// Inputs
clk
);
input clk;
output logic hit;
logic [31:0] addr;
int cyc;
initial addr = 32'h380;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef T_ASSERT_INSIDE_COND
addr <= 32'h380;
`elsif T_ASSERT_INSIDE_COND_BAD
addr <= 32'h389;
`else
`error "Bad test define"
`endif
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always_comb begin
hit = 0;
unique case (addr[11:0]) inside
[12'h380 : 12'h388]: begin
hit = 1;
end
endcase
end
endmodule

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@ -0,0 +1,3 @@
[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_inside_cond.v:39: Verilog $stop
Aborting...

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@ -0,0 +1,25 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
top_filename("t/t_assert_inside_cond.v");
compile(
verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"],
);
execute(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;