Parse 'wait_order' and test, still unsupported.

src/verilog.l

@@ -584,7 +584,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "var"                 { FL; return yVAR; }
   "virtual"             { FL; return yVIRTUAL__LEX; }
   "void"                { FL; return yVOID; }
-  "wait_order"          { ERROR_RSVD_WORD("SystemVerilog 2005"); }
+  "wait_order"          { FL; return yWAIT_ORDER; }
   "wildcard"            { ERROR_RSVD_WORD("SystemVerilog 2005"); }
   "with"                { FL; return yWITH__LEX; }
   "within"              { FL; return yWITHIN; }

src/verilog.y

@@ -769,7 +769,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yVIRTUAL__anyID "virtual-then-identifier"
 %token<fl>              yVOID           "void"
 %token<fl>              yWAIT           "wait"
-//UNSUP %token<fl>      yWAIT_ORDER     "wait_order"
+%token<fl>              yWAIT_ORDER     "wait_order"
 %token<fl>              yWAND           "wand"
 %token<fl>              yWEAK           "weak"
 %token<fl>              yWEAK0          "weak0"
@@ -3596,9 +3596,12 @@ statement_item<nodep>:          // IEEE: statement_item
         |       yWAIT '(' expr ')' stmtBlock            { $$ = new AstWait{$1, $3, $5}; }
         |       yWAIT yFORK ';'                         { $$ = new AstWaitFork{$1}; }
         //                      // action_block expanded here
-        //UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' stmt %prec prLOWER_THAN_ELSE    { UNSUP }
+        |       yWAIT_ORDER '(' vrdList ')' stmt %prec prLOWER_THAN_ELSE
-        //UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' stmt yELSE stmt   { UNSUP }
+                        { $$ = nullptr; BBUNSUP($4, "Unsupported: wait_order"); }
-        //UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' yELSE stmt    { UNSUP }
+        |       yWAIT_ORDER '(' vrdList ')' stmt yELSE stmt
+                        { $$ = nullptr; BBUNSUP($4, "Unsupported: wait_order"); }
+        |       yWAIT_ORDER '(' vrdList ')' yELSE stmt
+                        { $$ = nullptr; BBUNSUP($4, "Unsupported: wait_order"); }
         //
         //                      // IEEE: procedural_assertion_statement
         |       procedural_assertion_statement          { $$ = $1; }

test_regress/t/t_wait_order.out

@@ -0,0 +1,20 @@
+%Error-UNSUPPORTED: t/t_wait_order.v:16:23: Unsupported: wait_order
+   16 |       wait_order (a, b) wif[0] = '1;
+      |                       ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_wait_order.v:19:23: Unsupported: wait_order
+   19 |       wait_order (b, a) nif[0] = '1;
+      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:23:23: Unsupported: wait_order
+   23 |       wait_order (a, b) else welse[1] = '1;
+      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:26:23: Unsupported: wait_order
+   26 |       wait_order (b, a) else nelse[1] = '1;
+      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:30:23: Unsupported: wait_order
+   30 |       wait_order (a, b) wif[2] = '1; else welse[2] = '1;
+      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:33:23: Unsupported: wait_order
+   33 |       wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
+      |                       ^
+%Error: Exiting due to

test_regress/t/t_wait_order.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    expect_filename => $Self->{golden_filename},
+    verilator_flags2 => ['--timing'],
+    fails => $Self->{vlt_all},
+    );
+
+ok(1);
+1;

test_regress/t/t_wait_order.v

@@ -0,0 +1,60 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t(/*AUTOARG*/);
+
+   event a, b, c;
+   bit   wif[10], welse[10];
+   bit   nif[10], nelse[10];
+
+   initial begin
+      wait_order (a, b) wif[0] = '1;
+   end
+   initial begin
+      wait_order (b, a) nif[0] = '1;
+   end
+
+   initial begin
+      wait_order (a, b) else welse[1] = '1;
+   end
+   initial begin
+      wait_order (b, a) else nelse[1] = '1;
+   end
+
+   initial begin
+      wait_order (a, b) wif[2] = '1; else welse[2] = '1;
+   end
+   initial begin
+      wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
+   end
+
+   initial begin
+      #10;
+      -> a;
+      #10;
+      -> b;
+      #10;
+      -> c;
+      #10;
+      // NOTE This hasn't been validated against other simulators
+      `checkd(wif[0], 1'b1);
+      `checkd(nif[0], 1'b0);
+
+      `checkd(welse[1], 1'b0);
+      `checkd(nelse[1], 1'b1);
+
+      `checkd(wif[2], 1'b1);
+      `checkd(welse[2], 1'b0);
+      `checkd(nif[2], 1'b0);
+      `checkd(nelse[2], 1'b1);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule