forked from github/verilator
Tests: Check queue typedef.
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@ -19,6 +19,13 @@ module t (/*AUTOARG*/
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integer i;
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typedef integer q_t[$];
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initial begin
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q_t iq;
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iq.push_back(42);
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end
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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