From 5b532a181230eb3a6be19e1733950997acb17302 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 25 Apr 2012 18:17:10 -0400
Subject: [PATCH] Fix generate if, broke in earlier committ, bug492. Merge from
 Bennett.

---
 src/V3Const.cpp                    |  6 ++-
 test_regress/t/t_gen_cond_const.pl | 19 ++++++++
 test_regress/t/t_gen_cond_const.v  | 71 ++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_gen_cond_const.pl
 create mode 100644 test_regress/t/t_gen_cond_const.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 1572eb143..31e982c44 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -369,7 +369,11 @@ private:
     // Extraction checks
     bool warnSelect(AstSel* nodep) {
 	AstNode* basefromp = AstArraySel::baseFromp(nodep);
-	if (m_doGenerate) V3Width::widthParamsEdit(nodep); // Never checked yet
+	if (m_doGenerate) {
+	    // Never checked yet
+	    V3Width::widthParamsEdit(nodep);
+	    nodep->iterateChildren(*this);	// May need "constifying"
+	}
 	if (AstNodeVarRef* varrefp = basefromp->castNodeVarRef()) {
 	    AstVar* varp = varrefp->varp();
 	    if (!varp->dtypep()) varp->v3fatalSrc("Data type lost");
diff --git a/test_regress/t/t_gen_cond_const.pl b/test_regress/t/t_gen_cond_const.pl
new file mode 100755
index 000000000..304357b8c
--- /dev/null
+++ b/test_regress/t/t_gen_cond_const.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["--language 1364-2001"]
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_cond_const.v b/test_regress/t/t_gen_cond_const.v
new file mode 100644
index 000000000..e23daf4db
--- /dev/null
+++ b/test_regress/t/t_gen_cond_const.v
@@ -0,0 +1,71 @@
+// DESCRIPTION: Verilator: Verilog Test for generate IF constants
+//
+// The given generate loop should have a constant expression as argument. This
+// test checks it really does evaluate as constant.
+
+// This file ONLY is placed into the Public Domain, for any use, without
+// warranty, 2012 by Jeremy Bennett.
+
+
+`define MAX_SIZE  4
+
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // Set the parameters, so that we use a size less than MAX_SIZE
+   test_gen
+     #(.SIZE (2),
+       .MASK (4'b1111))
+     i_test_gen (.clk (clk));
+
+   // This is only a compilation test, but for good measure we do one clock
+   // cycle.
+   integer count;
+
+   initial begin
+      count = 0;
+   end
+
+   always @(posedge clk) begin
+      if (count == 1) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+      else begin
+	 count = count + 1;
+      end
+   end
+
+endmodule // t
+
+
+module test_gen
+
+  #( parameter
+     SIZE = `MAX_SIZE,
+     MASK = `MAX_SIZE'b0)
+
+ (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // Generate blocks that rely on short-circuiting of the logic to avoid
+   // errors.
+   generate
+      if ((SIZE < 8'h04) && MASK[0]) begin
+	 always @(posedge clk) begin
+`ifdef TEST_VERBOSE
+	    $write ("Generate IF MASK[0] = %d\n", MASK[0]);
+`endif
+	 end
+      end
+   endgenerate
+
+endmodule