Commentary

README.adoc

@@ -22,7 +22,7 @@ endif::[]
 
 [cols="a,a",indent=0,frame="none"]
 |===
-^.^| *Welcome to Verilator, the fastest free Verilog HDL simulator.*
+^.^| *Welcome to Verilator, the fastest Verilog HDL simulator.*
 +++ <br/> +++ &bullet; Accepts synthesizable Verilog or SystemVerilog
 +++ <br/> +++ &bullet; Performs lint code-quality checks
 +++ <br/> +++ &bullet; Compiles into multithreaded {cpp}, or SystemC
@@ -56,7 +56,7 @@ endif::[]
 == What Verilator Does
 
 Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
-"Verilates" the specified synthesizable Verilog or SystemVerilog code by
+"Verilates" the specified Verilog or SystemVerilog code by
 reading it, performing lint checks, and optionally inserting assertion
 checks and coverage-analysis points.  It outputs single- or multi-threaded
 .cpp and .h files, the "Verilated" code.
@@ -72,30 +72,30 @@ Verilator may not be the best choice if you are expecting a full featured
 replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
 if you are looking for a behavioral Verilog simulator e.g. for a quick
 class project (we recommend http://iverilog.icarus.com[Icarus Verilog] for
-this.)  However, if you are looking for a path to migrate synthesizable
+this.)  However, if you are looking for a path to migrate SystemVerilog to
-Verilog to {cpp} or SystemC, and your team is comfortable writing just a
+{cpp} or SystemC, and your team is comfortable writing just a
 touch of {cpp} code, Verilator is the tool for you.
 
 == Performance
 
-Verilator does not simply convert Verilog HDL to {cpp} or SystemC.  Rather
+Verilator does not simply convert Verilog HDL to {cpp} or SystemC.  Rather,
-than only translate, Verilator compiles your code into a much faster
+Verilator compiles your code into a much faster optimized and optionally
-optimized and optionally thread-partitioned model, which is in turn wrapped
+thread-partitioned model, which is in turn wrapped inside a
-inside a {cpp}/SystemC/{cpp}-under-Python module.  The results are a compiled Verilog
+{cpp}/SystemC/{cpp}-under-Python module.  The results are a compiled
-model that executes even on a single-thread over 10x faster than standalone
+Verilog model that executes even on a single-thread over 10x faster than
-SystemC, and on a single thread is about 100 times faster than interpreted
+standalone SystemC, and on a single thread is about 100 times faster than
-Verilog simulators such as http://iverilog.icarus.com[Icarus
+interpreted Verilog simulators such as http://iverilog.icarus.com[Icarus
 Verilog]. Another 2-10x speedup might be gained from multithreading
 (yielding 200-1000x total over interpreted simulators).
 
 Verilator has typically similar or better performance versus the commercial
 Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence
 Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,
-Verilator is free, so you can spend on computes rather than licenses. Thus
+Verilator is open-sourced, so you can spend on computes rather than
-Verilator gives you more cycles/dollar than anything else available.
+licenses. Thus Verilator gives you the best cycles/dollar.
 
 For more information on how Verilator stacks up to some of the other
-commercial and free Verilog simulators, see the
+closed-sourced and open-sourced Verilog simulators, see the
 https://www.veripool.org/verilog_sim_benchmarks.html[Verilog Simulator
 Benchmarks].  (If you benchmark Verilator, please see the notes in the
 https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)], and also