Update URLs to https://verilator.org

Makefile.in

@@ -3,7 +3,7 @@
 #
 # This file is part of Verilator.
 #
-# Code available from: http://www.veripool.org/verilator
+# Code available from: https://verilator.org
 #
 #*****************************************************************************
 #
@@ -472,7 +472,7 @@ install-msg:
 	@echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples"
 	@echo
 	@echo "For documentation see 'man verilator' or 'verilator --help'"
-	@echo "For forums and to report bugs see http://www.veripool.org/verilator"
+	@echo "For forums and to report bugs see https://verilator.org"
 	@echo
 
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in

bin/verilator

@@ -4832,9 +4832,8 @@ debugging enabled.  The full set of test options can be seen by running
 driver.pl --help as shown above.
 
 Finally, report the bug using the bug tracker at
-L<http://www.veripool.org/verilator>.  The bug will become publicly
+L<https://verilator.org/issues>.  The bug will become publicly visible; if
-visible; if this is unacceptable, mail the bug report to
+this is unacceptable, mail the bug report to C<wsnyder@wsnyder.org>.
-C<wsnyder@wsnyder.org>.
 
 
 =head1 HISTORY
@@ -4872,7 +4871,7 @@ faster than many popular commercial simulators.
 
 =head1 AUTHORS
 
-When possible, please instead report bugs to L<http://www.veripool.org/>.
+When possible, please instead report bugs to L<https://verilator.org/issues>.
 
 Wilson Snyder <wsnyder@wsnyder.org>
 
@@ -4955,7 +4954,7 @@ remain anonymous.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.org/>.
+The latest version is available from L<https://verilator.org>.
 
 Copyright 2003-2019 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of

bin/verilator_coverage

@@ -269,7 +269,7 @@ Specifies a module search directory.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.org/>.
+The latest version is available from L<https://verilator.org>.
 
 Copyright 2003-2019 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of

bin/verilator_difftree

@@ -234,7 +234,7 @@ Do not show differences in line numbering.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.org/verilator>.
+The latest version is available from L<https://verilator.org>.
 
 Copyright 2005-2019 by Wilson Snyder.  This package is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser

bin/verilator_gantt

@@ -538,7 +538,7 @@ verilator_gantt.vcd.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.org/>.
+The latest version is available from L<https://verilator.org>.
 
 Copyright 2018-2019 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser

bin/verilator_profcfunc

@@ -228,7 +228,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.org/>.
+The latest version is available from L<https://verilator.org>.
 
 Copyright 2007-2019 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser

configure.ac

@@ -7,8 +7,8 @@
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
 AC_INIT([Verilator],[4.020 devel],
-        [https://www.veripool.org/verilator],
+        [https://verilator.org],
-        [verilator],[https://www.veripool.org/verilator])
+        [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
 # and commit using "devel release" or "Version bump" message
 

docs/CONTRIBUTING.adoc

@@ -8,10 +8,10 @@ contributions flow more efficiently.
 ==== Did you find a bug?
 
 * Please **Ensure the bug was not already reported** by searching
-  https://www.veripool.org/projects/verilator/issues[Verilator Issues].
+  https://verilator.org/issues[Verilator Issues].
 
 * If you're unable to find an open issue addressing the problem,
-  https://www.veripool.org/projects/verilator/issues/new[open a new issue].
+  https://verilator.org/issues/new[open a new issue].
 
 ** Be sure to include a **code sample** or an **executable test case**
    demonstrating the bug and expected behavior that is not occurring.
@@ -22,8 +22,7 @@ contributions flow more efficiently.
 
 ==== Did you write a patch that fixes a bug?
 
-* Please https://www.veripool.org/projects/verilator/issues/new[Open a new
+* Please https://verilator.org/issues/new[Open a new issue].
-  issue].
 
 * You may attach a patch to the issue, or (preferred) may point to a GitHub
   repository branch within your GitHub account.
@@ -66,11 +65,12 @@ contributions flow more efficiently.
 
 ==== Do you have questions?
 
-* Please see the
+* Please see FAQ section and rest of the
-  https://www.veripool.org/projects/verilator/wiki/Faq[Verilator FAQ].
+  https://verilator.org/verilator_doc.html[Verilator manual],
+  or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)].
 
 * Ask any question in the
-  https://www.veripool.org/projects/verilator/boards[Verilator forums].
+  https://verilator.org/forum[Verilator forum].
 
 ==== Code of Conduct
 

docs/Makefile.in

@@ -3,7 +3,7 @@
 #
 # This file is part of Verilator.
 #
-# Code available from: http://www.veripool.org/verilator
+# Code available from: https://verilator.org
 #
 #*****************************************************************************
 #

include/verilated.cpp

@@ -19,7 +19,7 @@
 ///     This file must be compiled and linked against all objects
 ///     created from Verilator.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //=========================================================================
 

include/verilated.h

@@ -20,7 +20,7 @@
 ///     all C++ files it generates.  It contains standard macros and
 ///     classes required by the Verilated code.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated.v

@@ -1,6 +1,6 @@
 //*************************************************************************
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

include/verilated_config.h.in

@@ -16,7 +16,7 @@
 /// \file
 /// \brief Verilator: Auto version information include for all Verilated C files
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_dpi.cpp

@@ -19,7 +19,7 @@
 ///     This file must be compiled and linked against all objects
 ///     created from Verilator or called by Verilator that use the DPI.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //=========================================================================
 

include/verilated_dpi.h

@@ -20,7 +20,7 @@
 ///     all C++ files it generates where DPI is used.  It contains
 ///     DPI interface functions required by the Verilated code.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_heavy.h

@@ -21,7 +21,7 @@
 ///     heavyweight types are required; these contents are not part of
 ///     verilated.h to save compile time when such types aren't used.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_imp.h

@@ -16,7 +16,7 @@
 /// \file
 /// \brief Verilator: Implementation Header, only for verilated.cpp internals.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //=========================================================================
 

include/verilated_sc.h

@@ -19,7 +19,7 @@
 ///     This file is included automatically by Verilator at the top of
 ///     all SystemC files it generates.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_sym_props.h

@@ -24,7 +24,7 @@
 ///
 ///     These classes are thread safe, and read only.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_syms.h

@@ -23,7 +23,7 @@
 ///     These classes are thread safe and read only. It is constructed only
 ///     when a model is built (from the main thread).
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

include/verilated_unordered_set_map.h

@@ -3,7 +3,7 @@
 // DESCRIPTION: Verilator: pre-C++11 replacements for std::unordered_set
 //                         and std::unordered_map.
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

include/verilated_vpi.cpp

@@ -21,7 +21,7 @@
 ///
 ///     Use "verilator --vpi" to add this to the Makefile for the linker.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //=========================================================================
 

include/verilated_vpi.h

@@ -19,7 +19,7 @@
 ///     This file must be compiled and linked against all objects
 ///     created from Verilator or called by Verilator that use the VPI.
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //=========================================================================
 

include/verilatedos.h

@@ -22,7 +22,7 @@
 ///     config_build.h.in, code needed by Verilated code only goes into
 ///     verilated.h, and code needed by both goes here (verilatedos.h).
 ///
-/// Code available from: http://www.veripool.org/verilator
+/// Code available from: https://verilator.org
 ///
 //*************************************************************************
 

src/Makefile.in

@@ -3,7 +3,7 @@
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.org/verilator
+# Code available from: https://verilator.org
 #
 #*****************************************************************************
 #

src/Makefile_obj.in

@@ -3,7 +3,7 @@
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.org/verilator
+# Code available from: https://verilator.org
 #
 #*****************************************************************************
 #

src/V3Active.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Active.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3ActiveTop.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3ActiveTop.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Assert.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Assert.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion expansion
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3AssertPre.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3AssertPre.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion pre-expansion
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Ast.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Ast.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3AstConstOnly.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3AstNodes.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3AstNodes.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Begin.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Begin.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Branch.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Branch.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Broken.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Broken.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3CCtors.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Generate C language constructors and AstCReset nodes.
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3CCtors.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit CFunc's for class construction and configuration
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Case.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Case.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Cast.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Cast.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Cdc.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Clock Domain Crossing Lint
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Cdc.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Changed.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for changed nodes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Changed.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Clean.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for clean nodes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Clean.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Clock.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Clock.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Combine.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Combine.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Config.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Configuration Files
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Config.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Configuration Files
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Const.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Constant folding
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Const.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Propagate constants across AST
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Coverage.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Netlist (top level) functions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Coverage.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Coverage modules/signals together
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3CoverageJoin.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Netlist (top level) functions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3CoverageJoin.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Coverage modules/signals together
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Dead.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead code elimination
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Dead.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead branch elimination
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Delayed.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Delayed.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Depth.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Depth.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3DepthBlock.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3DepthBlock.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Descope.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Descope.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitC.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitC.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ code for module tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitCBase.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitCInlines.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitCMake.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit CMake file list
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitCMake.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit CMake file list
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitCSyms.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitMk.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitMk.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitV.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog from tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitV.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog code for module tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitXml.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog from tree
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3EmitXml.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit XML code
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Error.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Error.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Expand.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for expand nodes
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3Expand.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Expansion of wide operator macros to C operators
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3File.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3File.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3FileLine.cpp

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //

src/V3FileLine.h

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.org/verilator
+// Code available from: https://verilator.org
 //
 //*************************************************************************
 //