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Fix min/typ/max internal error

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Wilson Snyder 2023-03-14 20:40:58 -04:00
parent 0fc5d37901
commit 56de6f1a9f
1 changed files with 1 additions and 1 deletions
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src/verilog.y
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@ -2944,7 +2944,7 @@ delay_control<delayp>: //== IEEE: delay_control
| '#' '(' minTypMax ',' minTypMax ')' | '#' '(' minTypMax ',' minTypMax ')'
{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); } { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')' | '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); } { $$ = new AstDelay{$<fl>1, $5, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
; ;
delay_value<nodeExprp>: // ==IEEE:delay_value delay_value<nodeExprp>: // ==IEEE:delay_value