forked from github/verilator
Fix bad-syntax crashes, bug1586, bug1587.
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Changes
@ -27,7 +27,7 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix multithreaded yield behavior when no work. [Patrick Stewart]
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**** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563,
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bug1573-1577, bug1582-1585, bug1589-1591. [Eric Rippey]
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bug1573-1577, bug1582-1591. [Eric Rippey]
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**** Fix false CMPCONST/UNSIGNED warnings on "inside", bug1581. [Mitch Hayenga]
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@ -173,38 +173,48 @@ class SliceVisitor : public AstNVisitor {
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UINFO(9, " Bi-Eq/Neq expansion "<<nodep<<endl);
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if (AstUnpackArrayDType* adtypep = VN_CAST(fromDtp, UnpackArrayDType)) {
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AstNodeBiop* logp = NULL;
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for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) {
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// EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
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AstNodeBiop* clonep
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= VN_CAST(nodep->cloneType
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(new AstArraySel(nodep->fileline(),
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nodep->lhsp()->cloneTree(false),
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index),
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new AstArraySel(nodep->fileline(),
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nodep->rhsp()->cloneTree(false),
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index)),
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NodeBiop);
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if (!logp) logp = clonep;
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else {
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switch (nodep->type()) {
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case AstType::atEq: // FALLTHRU
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case AstType::atEqCase:
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logp = new AstLogAnd(nodep->fileline(), logp, clonep);
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break;
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case AstType::atNeq: // FALLTHRU
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case AstType::atNeqCase:
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logp = new AstLogOr(nodep->fileline(), logp, clonep);
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break;
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default:
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nodep->v3fatalSrc("Unknown node type processing array slice");
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break;
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if (!VN_IS(nodep->lhsp()->dtypep()->skipRefp(), NodeArrayDType)) {
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nodep->lhsp()->v3error("Slice operatator "<<nodep->lhsp()->prettyTypeName()
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<<" on non-slicable (e.g. non-vector) left-hand-side operand");
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}
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else if (!VN_IS(nodep->rhsp()->dtypep()->skipRefp(), NodeArrayDType)) {
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nodep->rhsp()->v3error("Slice operatator "<<nodep->rhsp()->prettyTypeName()
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<<" on non-slicable (e.g. non-vector) right-hand-side operand");
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}
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else {
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for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) {
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// EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
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AstNodeBiop* clonep
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= VN_CAST(nodep->cloneType
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(new AstArraySel(nodep->fileline(),
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nodep->lhsp()->cloneTree(false),
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index),
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new AstArraySel(nodep->fileline(),
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nodep->rhsp()->cloneTree(false),
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index)),
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NodeBiop);
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if (!logp) logp = clonep;
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else {
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switch (nodep->type()) {
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case AstType::atEq: // FALLTHRU
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case AstType::atEqCase:
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logp = new AstLogAnd(nodep->fileline(), logp, clonep);
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break;
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case AstType::atNeq: // FALLTHRU
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case AstType::atNeqCase:
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logp = new AstLogOr(nodep->fileline(), logp, clonep);
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break;
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default:
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nodep->v3fatalSrc("Unknown node type processing array slice");
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break;
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}
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}
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}
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UASSERT_OBJ(logp, nodep, "Unpacked array with empty indices range");
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nodep->replaceWith(logp);
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pushDeletep(nodep); VL_DANGLING(nodep);
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nodep = logp;
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}
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UASSERT_OBJ(logp, nodep, "Unpacked array with empty indices range");
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nodep->replaceWith(logp);
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pushDeletep(nodep); VL_DANGLING(nodep);
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nodep = logp;
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}
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iterateChildren(nodep);
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}
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5
test_regress/t/t_fuzz_eqne_bad.out
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5
test_regress/t/t_fuzz_eqne_bad.out
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@ -0,0 +1,5 @@
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%Error: t/t_fuzz_eqne_bad.v:11: Slice operatator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand
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: ... In instance t.b
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initial c = (a != &b);
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^
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%Error: Exiting due to
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18
test_regress/t/t_fuzz_eqne_bad.pl
Executable file
18
test_regress/t/t_fuzz_eqne_bad.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(linter => 1);
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lint(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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12
test_regress/t/t_fuzz_eqne_bad.v
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12
test_regress/t/t_fuzz_eqne_bad.v
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@ -0,0 +1,12 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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//bug1587
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module t;
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reg a[0];
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reg b;
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reg c;
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initial c = (a != &b);
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endmodule
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