diff --git a/Changes b/Changes
index bcbbbb381..b0e545ccd 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,8 @@ Verilator 4.225 devel
**Minor:**
* Add --future0 and --future1 options.
+* Improve Verilation speed with --threads on large designs. [Geza Lore]
+* Rename trace rolloverSize() (#3570).
* Fix incorrect bit op tree optimization (#3470). [algrobman]
* Fix empty string arguments to display (#3484). [Grulfen]
* Fix table misoptimizing away display (#3488). [Stefan Post]
@@ -21,9 +23,7 @@ Verilator 4.225 devel
* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
* Fix segfault exporting non-existant package (#3535).
* Fix case statement comparing string literal (#3544). [Gustav Svensk]
-* Fix --hierarchical with order-based pin connections (#3583). [Kelin9298]
-* Improve Verilation speed with --threads on large designs. [Geza Lore]
-* Rename trace rolloverSize() (#3570).
+* Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298]
Verilator 4.224 2022-06-19
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index d84f80aba..02e6b439b 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1500,6 +1500,10 @@ private:
refp, nullptr /*classOrPackagep*/);
symp->exported(false);
refp->pinNum(nodep->pinNum());
+ // Put the variable where the port is, so that variables stay
+ // in pin number sorted order. Otherwise hierarchical or XML
+ // may botch by-position instances.
+ nodep->addHereThisAsNext(refp->unlinkFrBack());
}
// Ports not needed any more
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
diff --git a/test_regress/t/t_hier_bynum.v b/test_regress/t/t_hier_bynum.v
index 4f930143d..fe76f1e8f 100644
--- a/test_regress/t/t_hier_bynum.v
+++ b/test_regress/t/t_hier_bynum.v
@@ -3,11 +3,11 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2022 by Wilson Snyder.
-module flop (
- output reg q,
- input wire d,
- input wire clk
- );
+module flop (q, d, clk);
+ // No AUTOARG; order of below is different from port order above
+ input wire clk;
+ output reg q;
+ input wire d;
// verilator hier_block
diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out
index 4484513c6..8fb6190c9 100644
--- a/test_regress/t/t_udp_bad.out
+++ b/test_regress/t/t_udp_bad.out
@@ -9,10 +9,10 @@
%Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1'
10 | udp_x x (a, b);
| ^
-%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules
- 15 | tri a_bad;
- | ^~~~~
%Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules
17 | output c_bad;
| ^~~~~
+%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules
+ 15 | tri a_bad;
+ | ^~~~~
%Error: Exiting due to
diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out
index 50968cab7..11cff436a 100644
--- a/test_regress/t/t_xml_first.out
+++ b/test_regress/t/t_xml_first.out
@@ -18,67 +18,67 @@
-
-
-
-
+
+
+
+
-
+
-
+
-
+
-
+
-
+
-
+
-
-
-
-
-
-
+
+
+
+
+
+
-
-
-
+
+
+
-
+
-
-
-
+
+
+
-
-
+
+
diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out
index eae232855..bc2e4f9b8 100644
--- a/test_regress/t/t_xml_flat.out
+++ b/test_regress/t/t_xml_flat.out
@@ -15,99 +15,99 @@
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
-
+
+
+
-
-
-
-
-
-
+
+
+
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
-
+
+
+
-
-
+
+