diff --git a/Changes b/Changes index 6c81a7e30..47d4a3257 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.913 devel +**** The internal test_verilated test directory is moved to be part of test_regress. + * Verilator 3.912 2017-09-23 diff --git a/Makefile.in b/Makefile.in index a7acd8afe..2381ebf7f 100644 --- a/Makefile.in +++ b/Makefile.in @@ -101,7 +101,7 @@ PACKAGE_VERSION = @PACKAGE_VERSION@ SHELL = /bin/sh -SUBDIRS = src test_verilated test_c test_sc test_regress +SUBDIRS = src test_c test_sc test_regress INFOS = README README.html README.pdf internals.txt internals.html \ internals.pdf verilator.txt verilator.html verilator.pdf \ @@ -129,7 +129,6 @@ DISTFILES_INC = $(INFOS) .gitignore Artistic COPYING COPYING.LESSER \ src/*.pl src/*.pod \ test_*/.*ignore test_*/Makefile* test_*/*.cpp \ test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \ - test_verilated/vgen*.pl \ test_regress/t/t*/*.sv* \ test_regress/t/t*/*.v* \ test_regress/t/t*/*/*.sv* \ @@ -187,7 +186,7 @@ msg_test: all_nomsg .PHONY:test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users -test: test_c test_sc test_verilated test_regress +test: test_c test_sc test_regress else test: test_c test_sc endif @@ -204,8 +203,6 @@ test_sc: all_nomsg @(cd test_sc && $(MAKE)) test_sc_debug: all_nomsg @(cd test_sc && $(MAKE) test_debug) -test_verilated: all_nomsg - @(cd test_verilated && $(MAKE)) test_regress: all_nomsg @(cd test_regress && $(MAKE)) @@ -468,6 +465,7 @@ clean mostlyclean distclean maintainer-clean:: rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas rm -f *.tex + rm -rf test_verilated/obj_dir distclean maintainer-clean:: rm -f Makefile config.status config.cache config.log TAGS diff --git a/README.pod b/README.pod index a04ee4b57..519d45750 100644 --- a/README.pod +++ b/README.pod @@ -193,7 +193,6 @@ The directories in the kit after de-taring are as follows: test_v => Example Verilog code for other test dirs test_c => Example Verilog->C++ conversion test_sc => Example Verilog->SystemC conversion - test_verilated => Internal tests test_regress => Internal tests =head1 LIMITATIONS diff --git a/doxygen.config b/doxygen.config index 9a29b3c98..7a21434c2 100644 --- a/doxygen.config +++ b/doxygen.config @@ -635,8 +635,7 @@ INPUT = doxygen-mainpage \ test_c \ test_regress \ test_sc \ - test_v \ - test_verilated + test_v # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is diff --git a/internals.pod b/internals.pod index 2f4e40172..bd2e3fbca 100644 --- a/internals.pod +++ b/internals.pod @@ -485,10 +485,10 @@ be warning free. =item --enable-longtests -In addition to the standard C, SystemC tests also run the tests in the -C and C directories when using I. -This is disabled by default as SystemC installation problems would -otherwise falsely indicate a Verilator problem. +In addition to the standard C, SystemC examples, also run the tests in the +C directory when using I. This is disabled by +default as SystemC installation problems would otherwise falsely indicate a +Verilator problem. =back diff --git a/test_regress/t/t_vgen.pl b/test_regress/t/t_vgen.pl new file mode 100755 index 000000000..672833184 --- /dev/null +++ b/test_regress/t/t_vgen.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +top_filename("$Self->{obj_dir}/vgen.v"); + +$Self->run(cmd=>["./vgen.pl", + "-o $Self->{top_filename}", + #"--seed 0", + ]); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_verilated/vgen.pl b/test_regress/vgen.pl similarity index 97% rename from test_verilated/vgen.pl rename to test_regress/vgen.pl index 4039bc523..abdfe7ce7 100755 --- a/test_verilated/vgen.pl +++ b/test_regress/vgen.pl @@ -200,6 +200,7 @@ foreach my $op (keys %ops2) { my $opt_seed=5; our $Opt_NumOps = 30; our $Opt_Depth = 4; +our $Opt_Output; our $Opt_Signed = 1; our $Opt_Raise; our $Opt_BlockStmts = 2; @@ -211,6 +212,7 @@ if (! GetOptions ( "depth=i" => \$Opt_Depth, "blockstmts=i"=> \$Opt_BlockStmts, "numops=i" => \$Opt_NumOps, + "o=s" => \$Opt_Output, "raise=i" => \$Opt_Raise, "seed=i" => \$opt_seed, "signed!" => \$Opt_Signed, @@ -229,7 +231,8 @@ srand($opt_seed); init(); selftest(); gentest(); -write_output_v("vgen.v"); +$Opt_Output or die "%Error: Need -o option,"; +write_output_v($Opt_Output); #---------------------------------------------------------------------- @@ -468,10 +471,9 @@ sub write_output_v { my $fh = IO::File->new($filename, "w") or die("%Error: $! $filename,\n"); print $fh "// Created by: $Rerun_Args\n"; - print $fh "module vgen (clk, check, done);\n"; + print $fh "module vgen (clk);\n"; print $fh " input clk;\n"; - print $fh " input check;\n"; - print $fh " output done;\n"; + print $fh " reg check; initial check = '0;\n"; print $fh ' initial $write("\n*** Vgen.v starting, seed = ',$opt_seed,'\n");',"\n"; print $fh " // verilator lint_off UNSIGNED\n"; @@ -519,21 +521,27 @@ sub write_output_v { } } - print $fh "\n"; - print $fh " reg done; initial done=1'b0;\n"; - print $fh " reg ddone; initial ddone=1'b0;\n"; + print $fh "\n"; + print $fh " parameter [31:0] CYCLES /*verilator public*/ = $cycles;\n"; + print $fh "\n"; + print $fh " integer cyc; initial cyc = 0;\n"; print $fh " always @(posedge clk) begin\n"; - print $fh " if (check) begin\n"; - print $fh " done <= 1'b1;\n"; + print $fh "`ifdef TEST_VERBOSE\n"; + print $fh ' $write("[%0t] cyc=%0d check=%d\n", $time, cyc, check);',"\n"; + print $fh "`endif\n"; + print $fh " cyc <= cyc + 1;\n"; + print $fh " if (cyc < CYCLES) begin\n"; + print $fh " check <= 1'b0;\n"; print $fh " end\n"; - print $fh " if (done && !ddone) begin\n"; - print $fh " ddone <= 1'b1;\n"; - print $fh ' $write("*-* All Finished *-*\n");',"\n"; + print $fh " else if (cyc >= CYCLES) begin\n"; + print $fh " check <= 1'b1;\n"; + print $fh " if (cyc >= (CYCLES+10)) begin\n"; + print $fh ' $write("*-* All Finished *-*\n");',"\n"; + print $fh ' $finish;',"\n"; + print $fh " end\n"; print $fh " end\n"; print $fh " end\n"; - print $fh "\n"; - print $fh " parameter [31:0] CYCLES /*verilator public*/ = $cycles;\n"; print $fh "endmodule\n"; $fh->close(); @@ -978,7 +986,7 @@ vgen.pl - Generate random verilog code =head1 SYNOPSIS - vgen.pl + vgen.pl -o vgen.v =head1 DESCRIPTION @@ -1009,6 +1017,10 @@ down to a NOP. Number of operations to create. +=item -o I + +Specify output filename. + =item --raise Pick the specified number of random opcodes, and raise their frequency. @@ -1044,6 +1056,6 @@ Wilson Snyder ###################################################################### ### Local Variables: -### compile-command: "./vgen.pl --depth=10 --blockstmts=10" -### compile-command: "make " +### compile-command: "./vgen.pl --depth=10 --blockstmts=10 -o obj_dir/vgen.v" +### compile-command: "v4make test_regress/t/t_vgen.pl " ### End: diff --git a/test_verilated/.gitignore b/test_verilated/.gitignore deleted file mode 100644 index 8ae794a39..000000000 --- a/test_verilated/.gitignore +++ /dev/null @@ -1,8 +0,0 @@ -*.old -obj_dir -vgen.v -simv* -*.key -csrc -*.log -INCA_libs diff --git a/test_verilated/Makefile b/test_verilated/Makefile deleted file mode 100644 index fd3c353c9..000000000 --- a/test_verilated/Makefile +++ /dev/null @@ -1,123 +0,0 @@ -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside source directory -# -# This calls the object directory makefile. That allows the objects to -# be placed in the "current directory" which simplifies the Makefile. -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#****************************************************************************/ - -default: test - -# This must point to the root of the VERILATOR kit -VERILATOR_ROOT := $(shell pwd)/.. -export VERILATOR_ROOT - -VERILATOR_NCVERILOG ?= ncverilog -VERILATOR_VCS ?= vcs - -# Pick up PERL and other variable settings -include $(VERILATOR_ROOT)/include/verilated.mk - -VERILATOR_SW += -ifeq ($(VERILATOR_NO_DEBUG),) - VERILATOR_SW += --debug --no-dump-tree -endif - -PERL_PACKAGES_OK := $(shell $(PERL) -e 'eval "use Bit::Vector; print 1;";') - -###################################################################### - -default: test - -ifneq ($(PERL_PACKAGES_OK),1) -test:: nopackages -else - ifneq ($(VCS_HOME),) -test:: vcs - else -test:: novcs - endif - - ifneq ($(NC_ROOT),) -test:: nc - else -test:: nonc - endif - -test:: vlt -endif - -vgen.v: ./vgen.pl - $(PERL) vgen.pl $(VGEN_FLAGS) - -# We ulimit cpu time, as some cases make gcc 3.3.4 hang -random: - -rm -rf obj_dir/Vgen* obj_dir/simx - $(PERL) vgen.pl --seed=0 --numops=1000 --depth=4 --raise=4 - VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error VCS_HOME= NC_ROOT= bash -c "ulimit -t 120; $(MAKE) test" -# $(MAKE) nc - -random_forever: - while ( $(MAKE) random ) ; do \ - echo ; \ - done - -###################################################################### - -nopackages: - @echo "No perl Bit::Vector package installed." - @echo "Not running regression test." - -novcs: - @echo "No VCS simulator installed." - @echo "Not running VCS regression test." - -vcs: vcs_passed.log - -simv: vgen.v sim_main.v - vcs +cli -I +define+vcs+1 +v2k -q vgen.v sim_main.v - -vcs_passed.log : simv - -rm -f vcs_passed.log - ./simv -l sim.log - grep -q Finished sim.log && grep Finished sim.log > vcs_passed.log - -###################################################################### - -nonc: - @echo "No NC-Verilog simulator installed." - @echo "Not running NC-Verilog regression test." - -nc: nc_passed.log - -nc_passed.log: vgen.v sim_main.v - $(VERILATOR_NCVERILOG) +licqueue +define+ncverilog=1 -q vgen.v sim_main.v - -rm -f nc_passed.log - grep -q Finished ncverilog.log && grep Finished ncverilog.log > nc_passed.log - -###################################################################### - -vlt: prep compile vlt_passed.log - -prep: vgen.v $(VERILATOR_ROOT)/bin/verilator - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_SW) --cc vgen.v - -compile: - cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj - -vlt_passed.log vlt_run: prep compile - -rm -f vlt_passed.log sim.log - obj_dir/simx | tee sim.log - grep -q Finished sim.log && grep Finished sim.log > vlt_passed.log - -###################################################################### -maintainer-copy:: -clean mostlyclean distclean maintainer-clean:: - -rm -rf obj_dir *.log *.dmp *.vpd simv* *.key vgen.v csrc INCA_libs - diff --git a/test_verilated/Makefile_obj b/test_verilated/Makefile_obj deleted file mode 100644 index b9a400ef1..000000000 --- a/test_verilated/Makefile_obj +++ /dev/null @@ -1,31 +0,0 @@ -# -*- Makefile -*- -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside object directory -# -# This is executed in the object directory, and called by ../Makefile -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#***************************************************************************** - -default: simx -include Vvgen.mk - -####################################################################### -# Use sp_log.cpp, so we can get output in sim.log - -# Needed by tracing routines -CPPFLAGS += -DVL_DEBUG=1 -CPPFLAGS += $(CPPFLAGS_ADD) - -####################################################################### -# Linking final exe -- presumes have a sim_main.cpp - -simx: sim_main.o $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a - $(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt - -sim_main.o: sim_main.cpp $(VM_PREFIX).h diff --git a/test_verilated/sim_main.cpp b/test_verilated/sim_main.cpp deleted file mode 100644 index cace8209c..000000000 --- a/test_verilated/sim_main.cpp +++ /dev/null @@ -1,55 +0,0 @@ -// DESCRIPTION: Verilator Test: Top level main for invoking model -// -// Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. - -#include - -#include "Vvgen.h" -#include "Vvgen_vgen.h" // For v - -Vvgen *top; - -vluint64_t main_time = 0; - -double sc_time_stamp () { - return main_time; -} - -int main(int argc, char **argv, char **env) { - Verilated::commandArgs(argc, argv); - Verilated::debug(0); // We compiled with it on for testing, turn it back off - - top = new Vvgen; - top->check = 0; - top->clk = 0; - -#define CYCTIME 10 - - // Cycle the interpreter - while (main_time < CYCTIME*top->vgen->CYCLES) { - top->eval(); - main_time += CYCTIME/2; - top->clk = !top->clk; - top->eval(); - main_time += CYCTIME/2; - top->clk = !top->clk; - } - - // Do a checking run - top->check = 1; - for (int i=0; i<10; i++) { - top->eval(); - main_time += CYCTIME/2; - top->clk = !top->clk; - top->eval(); - main_time += CYCTIME/2; - top->clk = !top->clk; - } - - top->final(); - - exit(0L); -} diff --git a/test_verilated/sim_main.v b/test_verilated/sim_main.v deleted file mode 100644 index f3291337e..000000000 --- a/test_verilated/sim_main.v +++ /dev/null @@ -1,42 +0,0 @@ -// DESCRIPTION: Verilator Test: Top level main for invoking model -// -// Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. - -module sim_main; - /*verilator public_module*/ - - reg clk; - reg check; - wire done; - - vgen vgen (/*AUTOINST*/ - // Outputs - .done (done), - // Inputs - .clk (clk), - .check (check)); - - integer i; - - initial begin - check = 1'b0; - clk = 1'b0; - for (i=0; i<10*vgen.CYCLES; i=i+1) begin - #5; - clk = ~clk; - #5; - clk = ~clk; - end - check = 1'b1; - for (i=0; i<10; i=i+1) begin - #5; - clk = ~clk; - #5; - clk = ~clk; - end - end - -endmodule