forked from github/verilator
Fix performance when mulithreaded on 1 CPU, bug1455.
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Changes
@ -28,6 +28,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix invalid XML output due to special chars, bug1444. [Kanad Kanhere]
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**** Fix invalid XML output due to special chars, bug1444. [Kanad Kanhere]
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**** Fix performance when mulithreaded on 1 CPU, bug1455. [Stefan Wallentowitz]
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* Verilator 4.014 2019-05-08
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* Verilator 4.014 2019-05-08
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@ -52,6 +52,10 @@ public:
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// METHODS
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// METHODS
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static vluint64_t yields() { return s_yields; }
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static vluint64_t yields() { return s_yields; }
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static void yieldThread() {
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++s_yields; // Statistics
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std::this_thread::yield();
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}
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// Block until notify() has occurred, then return.
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// Block until notify() has occurred, then return.
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// If notify() has already occurred, return immediately.
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// If notify() has already occurred, return immediately.
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@ -63,11 +67,10 @@ public:
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unsigned ct = 0;
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unsigned ct = 0;
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while (VL_UNLIKELY(!notified())) {
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while (VL_UNLIKELY(!notified())) {
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VL_CPU_RELAX();
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VL_CPU_RELAX();
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ct++;
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++ct;
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if (VL_UNLIKELY(ct > VL_LOCK_SPINS)) {
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if (VL_UNLIKELY(ct > VL_LOCK_SPINS)) {
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ct = 0;
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ct = 0;
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++s_yields; // Statistics
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yieldThread();
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std::this_thread::yield();
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}
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}
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}
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}
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}
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}
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@ -149,8 +152,14 @@ public:
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return m_upstreamDepsDone.load(std::memory_order_acquire) == target;
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return m_upstreamDepsDone.load(std::memory_order_acquire) == target;
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}
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}
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inline void waitUntilUpstreamDone(bool evenCycle) const {
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inline void waitUntilUpstreamDone(bool evenCycle) const {
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unsigned ct = 0;
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while (VL_UNLIKELY(!areUpstreamDepsDone(evenCycle))) {
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while (VL_UNLIKELY(!areUpstreamDepsDone(evenCycle))) {
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VL_CPU_RELAX();
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VL_CPU_RELAX();
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++ct;
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if (VL_UNLIKELY(ct > VL_LOCK_SPINS)) {
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ct = 0;
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VlNotification::yieldThread();
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}
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}
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}
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}
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}
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};
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};
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28
test_regress/t/t_bench_mux4k_onecpu.pl
Executable file
28
test_regress/t/t_bench_mux4k_onecpu.pl
Executable file
@ -0,0 +1,28 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(vltmt => 1);
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top_filename("t/t_bench_mux4k.v");
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compile(
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v_flags2 => ["--stats"],
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);
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if (`numactl --show` !~ /cpu/) {
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skip("No numactl available");
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} else {
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execute(
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run_env => 'numactl -m 0 -C 0,0,0,0,0,0,0,0',
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check_finished => 1,
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);
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ok(1);
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}
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1;
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