diff --git a/src/verilog.y b/src/verilog.y
index 3395594d2..a3ef77e66 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1810,8 +1810,8 @@ event_control<sentreep>:	// ==IEEE: event_control
 
 event_expression<senitemp>:	// IEEE: event_expression - split over several
 		senitem					{ $$ = $1; }
-	|	event_expression yOR senitem		{ $$ = $1;$1->addNextNull($3); }
-	|	event_expression ',' senitem		{ $$ = $1;$1->addNextNull($3); }	/* Verilog 2001 */
+	|	event_expression yOR senitem		{ $$ = $1->addNextNull($3)->castNodeSenItem(); }
+	|	event_expression ',' senitem		{ $$ = $1->addNextNull($3)->castNodeSenItem(); }	/* Verilog 2001 */
 	;
 
 senitem<senitemp>:		// IEEE: part of event_expression, non-'OR' ',' terms