forked from github/verilator
Fix test ignores
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@ -2421,7 +2421,7 @@ module etc. so that -y directory searching will work. This warning is
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printed for only the first mismatching module in any given file, and -v
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printed for only the first mismatching module in any given file, and -v
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library files are ignored.
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library files are ignored.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item DEFPARAM
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=item DEFPARAM
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@ -2429,7 +2429,7 @@ correctly.
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Warns that the "defparam" statement was deprecated in Verilog 2001 and all
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Warns that the "defparam" statement was deprecated in Verilog 2001 and all
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designs should now be using the #(...) format to specify parameters.
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designs should now be using the #(...) format to specify parameters.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item GENCLK
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=item GENCLK
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@ -2452,7 +2452,7 @@ Warns that if/if else statements have exceeded the depth specified with
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and priority if statements are ignored. Solutions include changing the
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and priority if statements are ignored. Solutions include changing the
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code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.
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code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item IMPERFECTSCH
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=item IMPERFECTSCH
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@ -2491,7 +2491,7 @@ Instead of using absolute paths, relative paths (preferably without any
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directory specified whatever) should be used, and +include used on the
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directory specified whatever) should be used, and +include used on the
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command line to specify the top include source directory.
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command line to specify the top include source directory.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item LITENDIAN
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=item LITENDIAN
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@ -2594,7 +2594,7 @@ Warns that the specified signal is never sourced. Verilator is fairly
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liberal in the usage calculations; making a signal public, or loading only
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liberal in the usage calculations; making a signal public, or loading only
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a single array element marks the entire signal as driven.
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a single array element marks the entire signal as driven.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item UNOPT
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=item UNOPT
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@ -2681,7 +2681,7 @@ Warns that the specified signal is never sinked. Verilator is fairly
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liberal in the usage calculations; making a signal public, or accessing
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liberal in the usage calculations; making a signal public, or accessing
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only a single array element marks the entire signal as used.
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only a single array element marks the entire signal as used.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item VARHIDDEN
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=item VARHIDDEN
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@ -2691,7 +2691,7 @@ the same name as a variable in the upper level module or begin/end block
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(thus hiding the upper variable from being able to be used.) Rename the
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(thus hiding the upper variable from being able to be used.) Rename the
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variable to avoid confusion when reading the code.
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variable to avoid confusion when reading the code.
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Disabled by default as this is a code style warning, it will simulate
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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correctly.
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=item WIDTH
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=item WIDTH
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@ -72,6 +72,7 @@ public:
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}
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}
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}
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}
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~UndrivenVarEntry() {}
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~UndrivenVarEntry() {}
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private:
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private:
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// METHODS
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// METHODS
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inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
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inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
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@ -284,7 +285,6 @@ public:
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// CONSTUCTORS
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// CONSTUCTORS
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UndrivenVisitor(AstNetlist* nodep) {
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UndrivenVisitor(AstNetlist* nodep) {
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m_markBoth = false;
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m_markBoth = false;
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AstNode::user1ClearTree(); // user1p() used on entire tree
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nodep->accept(*this);
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nodep->accept(*this);
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}
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}
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virtual ~UndrivenVisitor() {
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virtual ~UndrivenVisitor() {
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1
test_vcs/.gitignore
vendored
1
test_vcs/.gitignore
vendored
@ -5,6 +5,7 @@
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*.vcd
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*.vcd
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csrc
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csrc
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vcs.key
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vcs.key
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ucli.key
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*.daidir
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*.daidir
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simv
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simv
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obj_*
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obj_*
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@ -5,7 +5,7 @@
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# This calls the object directory makefile. That allows the objects to
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# This calls the object directory makefile. That allows the objects to
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# be placed in the "current directory" which simplifies the Makefile.
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# be placed in the "current directory" which simplifies the Makefile.
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#
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# Copyright 2003-2011 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# Version 2.0.
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@ -72,5 +72,5 @@ nc_passed.log: $(V_FILES) ../test_v/input.vc
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maintainer-copy::
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maintainer-copy::
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clean mostlyclean distclean maintainer-clean::
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clean mostlyclean distclean maintainer-clean::
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-rm -rf obj_dir *.log *.dmp *.vpd simv* vcs.key csrc INCA_libs
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-rm -rf obj_dir *.log *.dmp *.vpd simv* *.key csrc INCA_libs
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