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Fix test ignores

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This commit is contained in:
Wilson Snyder 2010-12-30 21:20:58 -05:00
parent b43299c8da
commit 4ca7f8834c
4 changed files with 11 additions and 10 deletions
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14
bin/verilator
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@ -2421,7 +2421,7 @@ module etc. so that -y directory searching will work. This warning is
printed for only the first mismatching module in any given file, and -v
library files are ignored.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item DEFPARAM
@ -2429,7 +2429,7 @@ correctly.
Warns that the "defparam" statement was deprecated in Verilog 2001 and all
designs should now be using the #(...) format to specify parameters.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item GENCLK
@ -2452,7 +2452,7 @@ Warns that if/if else statements have exceeded the depth specified with
and priority if statements are ignored. Solutions include changing the
code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item IMPERFECTSCH
@ -2491,7 +2491,7 @@ Instead of using absolute paths, relative paths (preferably without any
directory specified whatever) should be used, and +include used on the
command line to specify the top include source directory.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item LITENDIAN
@ -2594,7 +2594,7 @@ Warns that the specified signal is never sourced. Verilator is fairly
liberal in the usage calculations; making a signal public, or loading only
a single array element marks the entire signal as driven.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item UNOPT
@ -2681,7 +2681,7 @@ Warns that the specified signal is never sinked. Verilator is fairly
liberal in the usage calculations; making a signal public, or accessing
only a single array element marks the entire signal as used.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item VARHIDDEN
@ -2691,7 +2691,7 @@ the same name as a variable in the upper level module or begin/end block
(thus hiding the upper variable from being able to be used.) Rename the
variable to avoid confusion when reading the code.
Disabled by default as this is a code style warning, it will simulate
Disabled by default as this is a code style warning; it will simulate
correctly.
=item WIDTH

2
src/V3Undriven.cpp
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@ -72,6 +72,7 @@ public:
}
}
~UndrivenVarEntry() {}
private:
// METHODS
inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
@ -284,7 +285,6 @@ public:
// CONSTUCTORS
UndrivenVisitor(AstNetlist* nodep) {
m_markBoth = false;
AstNode::user1ClearTree(); // user1p() used on entire tree
nodep->accept(*this);
}
virtual ~UndrivenVisitor() {

1
test_vcs/.gitignore vendored
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@ -5,6 +5,7 @@
*.vcd
csrc
vcs.key
ucli.key
*.daidir
simv
obj_*

4
test_vcs/Makefile
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@ -5,7 +5,7 @@
# This calls the object directory makefile. That allows the objects to
# be placed in the "current directory" which simplifies the Makefile.
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# Copyright 2003-2011 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -72,5 +72,5 @@ nc_passed.log: $(V_FILES) ../test_v/input.vc
maintainer-copy::
clean mostlyclean distclean maintainer-clean::
-rm -rf obj_dir *.log *.dmp *.vpd simv* vcs.key csrc INCA_libs
-rm -rf obj_dir *.log *.dmp *.vpd simv* *.key csrc INCA_libs