Fix class wide member display (#2567).

Changes

@@ -15,6 +15,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix method calls to package class functions (#2565). [Peter Monsson]
 
+****  Fix class wide member display (#2567). [Nandu Raj P]
+
 
 * Verilator 4.100 2020-09-07
 

src/V3AstNodes.cpp

@@ -333,7 +333,7 @@ string AstVar::vlArgType(bool named, bool forReturn, bool forFunc, const string&
     string ostatic;
     if (isStatic() && namespc.empty()) ostatic = "static ";
 
-    VlArgTypeRecursed info = vlArgTypeRecurse(forFunc, dtypep());
+    VlArgTypeRecursed info = vlArgTypeRecurse(forFunc, dtypep(), false);
 
     string oname;
     if (named) {

src/V3AstNodes.h

@@ -2186,7 +2186,7 @@ public:
 private:
     class VlArgTypeRecursed;
     VlArgTypeRecursed vlArgTypeRecurse(bool forFunc, const AstNodeDType* dtypep,
-                                       bool compound = false) const;
+                                       bool compound) const;
 };
 
 class AstDefParam : public AstNode {

src/V3CUse.cpp

@@ -167,7 +167,14 @@ class CUseVisitor : public AstNVisitor {
                 stmt += comma;
                 comma = ", ";
                 stmt += itemp->origNameProtect();
-                stmt += ":\" + VL_TO_STRING(";
+                stmt += ":\" + ";
+                if (itemp->isWide()) {
+                    stmt += "VL_TO_STRING_W(";
+                    stmt += cvtToStr(itemp->widthWords());
+                    stmt += ", ";
+                } else {
+                    stmt += "VL_TO_STRING(";
+                }
                 stmt += itemp->nameProtect();
                 stmt += ");\n";
                 nodep->user1(true);  // So what we extend dumps this

test_regress/t/t_class_packed.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_class_packed.v

@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   //TODO sub #(.WIDTH(1)) w1;
+   //TODO sub #(.WIDTH(2)) w2;
+   //TODO sub #(.WIDTH(3)) w3;
+   //TODO sub #(.WIDTH(4)) w4;
+   sub #(.WIDTH(5)) w5;
+
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module sub ();
+   parameter WIDTH=5; // WIDTH >= 5 fails. WIDTH <= 4 passes
+
+   typedef struct packed {
+      logic [WIDTH-1:0] data;
+      } [15:0] w_t;
+
+   class WrReqQ;
+      w_t w;
+   endclass
+
+   initial begin
+      if ($bits(w_t) != WIDTH * 16) $stop;
+   end
+
+endmodule