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Follow other clock gating examples

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This commit is contained in:
Todd Strader 2020-02-21 05:47:00 -05:00
parent 120f62fe85
commit 4b4f10f5e6
3 changed files with 31 additions and 4 deletions
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20
test_regress/t/t_prot_lib.v
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@ -14,7 +14,7 @@ if (cyc > 0 && sig``_in != sig``_out) begin \
$stop; \
end
module t (/*AUTOARG*/
module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
// Inputs
clk
);
@ -90,8 +90,6 @@ module t (/*AUTOARG*/
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
accum_in <= accum_in + 5;
// 7 is the secret_value inside the secret module
accum_out_expect <= accum_in + accum_out_expect + 7;
`DRIVE(s1)
`DRIVE(s2)
`DRIVE(s8)
@ -125,6 +123,22 @@ module t (/*AUTOARG*/
end
end
logic possibly_gated_clk;
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign possibly_gated_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign possibly_gated_clk = clk;
end
always @(posedge possibly_gated_clk) begin
// 7 is the secret_value inside the secret module
accum_out_expect <= accum_in + accum_out_expect + 7;
end
always @(*) begin
// XSim (and maybe all event simulators?) sees the moment where
// s1_in has not yet propagated to s1_out, however, they do always

1
test_regress/t/t_prot_lib_clk_gated.pl
View File

@ -49,6 +49,7 @@ while (1) {
compile(
verilator_flags2 => ["$secret_dir/secret.sv",
"-GGATED_CLK=1",
"-LDFLAGS",
"'-L$secret_prefix -lsecret -static'"],
xsim_flags2 => ["$secret_dir/secret.sv"],

14
test_regress/t/t_prot_lib_secret.v
View File

@ -32,7 +32,19 @@ module secret #(parameter GATED_CLK = 0)
initial $display("created %m");
wire the_clk = GATED_CLK != 0 ? clk & clk_en : clk;
logic the_clk;
generate
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign the_clk = clk;
end
endgenerate
always @(posedge the_clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end