From 486b6580d80f98e690cdb6b9ca902ea8191d3aef Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 29 Apr 2012 08:30:02 -0400 Subject: [PATCH] Internals: Rename VSignedState. Merge from dtype. No functional change. --- src/V3Ast.h | 17 +++++++++-------- src/V3AstNodes.h | 12 ++++++------ src/V3ParseImp.h | 2 +- src/verilog.y | 2 +- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/src/V3Ast.h b/src/V3Ast.h index 389ac5224..ccd353e35 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -61,12 +61,20 @@ public: //###################################################################### +enum VSignedState { + // This can't be in the fancy class as the lexer union will get upset + signedst_NOSIGN=0, signedst_UNSIGNED=1, signedst_SIGNED=2 +}; + +//###################################################################### + class AstNumeric { public: enum en { UNSIGNED, SIGNED, - DOUBLE + DOUBLE, + _ENUM_MAX // Leave last // Limited to 2 bits, unless change V3Ast's packing function }; enum en m_e; @@ -342,13 +350,6 @@ public: //###################################################################### -enum AstSignedState { - // This can't be in the fancy class as the lexer union will get upset - signedst_NOSIGNED=0, signedst_UNSIGNED=1, signedst_SIGNED=2 -}; - -//###################################################################### - class AstVarType { public: enum en { diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index bf6feab27..464637c83 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -264,21 +264,21 @@ private: bool m_nosigned; // Implicit without sign int m_msb; // MSB when no range attached public: - AstBasicDType(FileLine* fl, AstBasicDTypeKwd kwd, AstSignedState signst=signedst_NOSIGNED) + AstBasicDType(FileLine* fl, AstBasicDTypeKwd kwd, VSignedState signst=signedst_NOSIGN) : AstNodeDType(fl) { init(kwd, signst, 0, NULL); } AstBasicDType(FileLine* fl, VFlagLogicPacked, int wantwidth) : AstNodeDType(fl) { - init(AstBasicDTypeKwd::LOGIC, signedst_NOSIGNED, wantwidth, NULL); + init(AstBasicDTypeKwd::LOGIC, signedst_NOSIGN, wantwidth, NULL); } AstBasicDType(FileLine* fl, VFlagBitPacked, int wantwidth) : AstNodeDType(fl) { - init(AstBasicDTypeKwd::BIT, signedst_NOSIGNED, wantwidth, NULL); + init(AstBasicDTypeKwd::BIT, signedst_NOSIGN, wantwidth, NULL); } // See also addRange in verilog.y private: - void init(AstBasicDTypeKwd kwd, AstSignedState signst, int wantwidth, AstRange* rangep) { + void init(AstBasicDTypeKwd kwd, VSignedState signst, int wantwidth, AstRange* rangep) { m_keyword = kwd; m_msb = 0; // Implicitness: // "parameter X" is implicit and sized from initial value, "parameter reg x" not @@ -288,7 +288,7 @@ private: if (!rangep && !wantwidth) m_implicit = true; // Also cleared if range added later m_keyword = AstBasicDTypeKwd::LOGIC; } - if (signst == signedst_NOSIGNED) { + if (signst == signedst_NOSIGN) { if (keyword().isSigned()) signst = signedst_SIGNED; else m_nosigned = true; } @@ -315,7 +315,7 @@ public: virtual string name() const { return m_keyword.ascii(); } AstRange* rangep() const { return op1p()->castRange(); } // op1 = Range of variable void rangep(AstRange* nodep) { setNOp1p(nodep); } - void setSignedState(AstSignedState signst) { + void setSignedState(VSignedState signst) { if (signst==signedst_UNSIGNED) numeric(AstNumeric::UNSIGNED); else if (signst==signedst_SIGNED) numeric(AstNumeric::SIGNED); } diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 163c52bae..d9fbded0c 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -55,7 +55,7 @@ struct V3ParseBisonYYSType { double cdouble; bool cbool; V3UniqState uniqstate; - AstSignedState signstate; + VSignedState signstate; V3ImportProperty iprop; V3ErrorCode::en errcodeen; diff --git a/src/verilog.y b/src/verilog.y index aca268c68..0b97f6b58 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1105,7 +1105,7 @@ non_integer_type: // ==IEEE: non_integer_type ; signingE: // IEEE: signing - plus empty - /*empty*/ { $$ = signedst_NOSIGNED; } + /*empty*/ { $$ = signedst_NOSIGN; } | signing { $$ = $1; } ;