From 479b497528d2c77ca0f40b08e78dcad44c38a56a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 7 Mar 2012 20:00:09 -0500 Subject: [PATCH] Tests: Add new tests from Iztok Jeras, bug446, bug450. --- test_regress/t/t_array_packed_literals.pl | 20 +++ test_regress/t/t_array_packed_literals.v | 119 +++++++++++++++ test_regress/t/t_array_packed_methods.pl | 20 +++ test_regress/t/t_array_packed_methods.v | 143 +++++++++++++++++++ test_regress/t/t_array_packed_write_read.pl | 20 +++ test_regress/t/t_array_packed_write_read.v | 143 +++++++++++++++++++ test_regress/t/t_hierarchy_identifier.pl | 18 +++ test_regress/t/t_hierarchy_identifier.v | 53 +++++++ test_regress/t/t_hierarchy_identifier_bad.pl | 18 +++ test_regress/t/t_hierarchy_identifier_bad.v | 53 +++++++ 10 files changed, 607 insertions(+) create mode 100755 test_regress/t/t_array_packed_literals.pl create mode 100644 test_regress/t/t_array_packed_literals.v create mode 100755 test_regress/t/t_array_packed_methods.pl create mode 100644 test_regress/t/t_array_packed_methods.v create mode 100755 test_regress/t/t_array_packed_write_read.pl create mode 100644 test_regress/t/t_array_packed_write_read.v create mode 100755 test_regress/t/t_hierarchy_identifier.pl create mode 100644 test_regress/t/t_hierarchy_identifier.v create mode 100755 test_regress/t/t_hierarchy_identifier_bad.pl create mode 100644 test_regress/t/t_hierarchy_identifier_bad.v diff --git a/test_regress/t/t_array_packed_literals.pl b/test_regress/t/t_array_packed_literals.pl new file mode 100755 index 000000000..2f21be6f8 --- /dev/null +++ b/test_regress/t/t_array_packed_literals.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug355"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_array_packed_literals.v b/test_regress/t/t_array_packed_literals.v new file mode 100644 index 000000000..fa3028327 --- /dev/null +++ b/test_regress/t/t_array_packed_literals.v @@ -0,0 +1,119 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 4; // address dimension size + localparam WB = 4; // bit dimension size + + localparam NO = 10; // number of access events + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]==0) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_bg = '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]==2) array_bg = '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]==3) array_bg = '{default:13}; + else if (cnt[30:2]==4) array_bg = '{2:15, default:13}; + else if (cnt[30:2]==5) array_bg = '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==6) array_bg = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + else if (cnt[30:2]==7) array_bg = '{WA { {WB/2-1{2'b10}} }}; + else if (cnt[30:2]==8) array_bg [WA/2-1:0 ] = '{WA/2{ {WB/2 {2'b10}} }}; + else if (cnt[30:2]==9) array_bg [WA -1:WA/2] = '{WA/2{ {WB/2 {2'b01}} }}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (array_bg !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==6) begin if (array_bg !== 16'b0110011001100110) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==7) begin if (array_bg !== 16'b0010001000100010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==8) begin if (array_bg !== 16'b10101010xxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==9) begin if (array_bg !== 16'bxxxxxxxx10101010) begin $display("%b", array_bg); $stop(); end end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]==0) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_lt = '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]==2) array_lt = '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]==3) array_lt = '{default:13}; + else if (cnt[30:2]==4) array_lt = '{1:15, default:13}; + else if (cnt[30:2]==5) array_lt = '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==6) array_lt = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + else if (cnt[30:2]==7) array_lt = '{WA { {WB/2-1{2'b10}} }}; + else if (cnt[30:2]==8) array_lt [0 :WA/2-1] = '{WA/2{ {WB/2 {2'b10}} }}; + else if (cnt[30:2]==9) array_lt [WA/2:WA -1] = '{WA/2{ {WB/2 {2'b01}} }}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (array_lt !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==6) begin if (array_lt !== 16'b0110011001100110) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==7) begin if (array_lt !== 16'b0010001000100010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==8) begin if (array_lt !== 16'b10101010xxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==9) begin if (array_lt !== 16'bxxxxxxxx10101010) begin $display("%b", array_lt); $stop(); end end + end + +endmodule diff --git a/test_regress/t/t_array_packed_methods.pl b/test_regress/t/t_array_packed_methods.pl new file mode 100755 index 000000000..f83806a29 --- /dev/null +++ b/test_regress/t/t_array_packed_methods.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug448"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_array_packed_methods.v b/test_regress/t/t_array_packed_methods.v new file mode 100644 index 000000000..3cfb77617 --- /dev/null +++ b/test_regress/t/t_array_packed_methods.v @@ -0,0 +1,143 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + integer slc = 0; // slice type + integer dim = 0; // dimension + integer wdt = 0; // width + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // calculation of dimention sizes + always @ (posedge clk) + begin + // slicing tipe counter + case (cnt[3:2]) + 2'd0 : begin slc = 0; end // full array + 2'd1 : begin slc = 1; end // half array + 2'd2 : begin slc = 2; end // single array element + default: begin slc = 0; end + endcase + // dimmension counter + case (cnt[1:0]) + 2'd0 : begin dim = 1; wdt = (slc==1) ? WA/2 + : (slc==2) ? 1 + : WA; end + 2'd1 : begin dim = 2; wdt = WB; end + 2'd2 : begin dim = 3; wdt = WC; end + default: begin dim = 0; wdt = 0; end + endcase + end + + always @ (posedge clk) + if (cnt[30:4]==1) begin + // big endian + if (cnt[3:2]==0) begin + // full array + if ($dimensions (array_bg) != 3) $stop; + if ($bits (array_bg) != WA*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_bg, dim) != wdt-1) $stop; + if ($right (array_bg, dim) != 0 ) $stop; + if ($low (array_bg, dim) != 0 ) $stop; + if ($high (array_bg, dim) != wdt-1) $stop; + if ($increment (array_bg, dim) != 1 ) $stop; + if ($size (array_bg, dim) != wdt ) $stop; + end + end else if (cnt[3:2]==1) begin + // half array + if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop; + if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop; + if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop; + if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop; + if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop; + if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop; + if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop; + end + end else if (cnt[3:2]==2) begin + // single array element + if ($dimensions (array_bg[0]) != 2) $stop; + if ($bits (array_bg[0]) != WB*WC) $stop; + if ((dim>=2)&&(dim<=3)) begin + if ($left (array_bg[0], dim-1) != wdt-1) $stop; + if ($right (array_bg[0], dim-1) != 0 ) $stop; + if ($low (array_bg[0], dim-1) != 0 ) $stop; + if ($high (array_bg[0], dim-1) != wdt-1) $stop; + if ($increment (array_bg[0], dim-1) != 1 ) $stop; + if ($size (array_bg[0], dim-1) != wdt ) $stop; + end + end + end else if (cnt[30:4]==2) begin + // little endian + if (cnt[3:2]==0) begin + // full array + if ($dimensions (array_lt) != 3) $stop; + if ($bits (array_lt) != WA*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_lt, dim) != 0 ) $stop; + if ($right (array_lt, dim) != wdt-1) $stop; + if ($low (array_lt, dim) != 0 ) $stop; + if ($high (array_lt, dim) != wdt-1) $stop; + if ($increment (array_lt, dim) != -1 ) $stop; + if ($size (array_lt, dim) != wdt ) $stop; + end + end else if (cnt[3:2]==1) begin + // half array + if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop; + if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop; + if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop; + if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop; + if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop; + if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop; + if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop; + end + end else if (cnt[3:2]==2) begin + // single array element + if ($dimensions (array_lt[0]) != 2) $stop; + if ($bits (array_lt[0]) != WB*WC) $stop; + if ((dim>=2)&&(dim<=3)) begin + if ($left (array_lt[0], dim-1) != 0 ) $stop; + if ($right (array_lt[0], dim-1) != wdt-1) $stop; + if ($low (array_lt[0], dim-1) != 0 ) $stop; + if ($high (array_lt[0], dim-1) != wdt-1) $stop; + if ($increment (array_lt[0], dim-1) != -1 ) $stop; + if ($size (array_lt[0], dim-1) != wdt ) $stop; + end + end + end + +endmodule diff --git a/test_regress/t/t_array_packed_write_read.pl b/test_regress/t/t_array_packed_write_read.pl new file mode 100755 index 000000000..74cef8faf --- /dev/null +++ b/test_regress/t/t_array_packed_write_read.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug446"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v new file mode 100644 index 000000000..93173b38a --- /dev/null +++ b/test_regress/t/t_array_packed_write_read.v @@ -0,0 +1,143 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 8; // address dimension size + localparam WB = 8; // bit dimension size + + localparam NO = 10; // number of access events + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} }; + else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_bg = {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] = {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_bg [WA -1:WA/2] = {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_bg [ 0 ] = {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_bg [WA -1 ] = {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] = {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] = {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] = {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] = {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end + else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end + else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end + else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end + else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end + else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} }; + else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_lt = {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_lt [0 :WA/2-1] = {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_lt [WA/2:WA -1] = {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_lt [0 ] = {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_lt [ WA -1] = {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_lt [0 ][0 ] = {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] = {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end + else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end + else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end + else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end + else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end + else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + end + +endmodule diff --git a/test_regress/t/t_hierarchy_identifier.pl b/test_regress/t/t_hierarchy_identifier.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_hierarchy_identifier.v b/test_regress/t/t_hierarchy_identifier.v new file mode 100644 index 000000000..2656922a2 --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter SIZE = 8; + + integer cnt = 0; + + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; + + genvar i; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==SIZE) begin : if_cnt_finish + $write("*-* All Finished *-*\n"); + $finish; + end : if_cnt_finish + + generate + for (i=0; i0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else + endgenerate + +endmodule : t diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier_bad.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_hierarchy_identifier_bad.v b/test_regress/t/t_hierarchy_identifier_bad.v new file mode 100644 index 000000000..e31eaf193 --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier_bad.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter SIZE = 8; + + integer cnt = 0; + + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; + + genvar i; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==SIZE) begin : if_cnt_finish + $write("*-* All Finished *-*\n"); + $finish; + end : if_cnt_finish_bad + + generate + for (i=0; i0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if_bad + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else_bad + endgenerate + +endmodule : t_bad