forked from github/verilator
Fix implying dotted wire names
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a547133efe
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46f70b1cbb
@ -805,7 +805,7 @@ private:
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if (nodep->castDot()) { // Not creating a simple implied type,
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if (nodep->castDot()) { // Not creating a simple implied type,
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// and implying something else would just confuse later errors
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// and implying something else would just confuse later errors
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}
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}
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if (nodep->castVarRef() || (nodep->castParseRef() && nodep->castParseRef()->start())) {
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else if (nodep->castVarRef() || (nodep->castParseRef() && nodep->castParseRef()->start())) {
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// To prevent user errors, we should only do single bit
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// To prevent user errors, we should only do single bit
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// implicit vars, however some netlists (MIPS) expect single
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// implicit vars, however some netlists (MIPS) expect single
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// bit implicit wires to get created with range 0:0 etc.
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// bit implicit wires to get created with range 0:0 etc.
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