diff --git a/Changes b/Changes
index c59d2a971..ed22849f4 100644
--- a/Changes
+++ b/Changes
@@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add circular typedef error, bug1388.  [Al Grant]
 
+****  Add unsupported for loops error, msg2692. [Yu Sheng Lin]
+
 ****  Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]
 
 ****  Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
diff --git a/src/verilog.y b/src/verilog.y
index ae7fe82a4..492da7f27 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2647,13 +2647,29 @@ assignment_pattern<patternp>:	// ==IEEE: assignment_pattern
 // "datatype id = x {, id = x }"  |  "yaId = x {, id=x}" is legal
 for_initialization<nodep>:	// ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
 	//			// IEEE: for_variable_declaration
-		data_type idAny/*new*/ '=' expr ';'
+		for_initializationItemList ';'		{ $$ = $1; }
+	//			// IEEE: 1800-2017 empty initialization
+	|	';'					{ $$ = NULL; }
+	;
+
+for_initializationItemList<nodep>:	// IEEE: [for_variable_declaration...]
+		for_initializationItem			{ $$ = $1; }
+	|	for_initializationItemList ',' for_initializationItem	{ $$ = $1; $<fl>2->v3error("Unsupported: for loop initialization after the first comma"); }
+	;
+
+for_initializationItem<nodep>:		// IEEE: variable_assignment + for_variable_declaration
+	//			// IEEE: for_variable_declaration
+		data_type idAny/*new*/ '=' expr
 			{ VARRESET_NONLIST(VAR); VARDTYPE($1);
 			  $$ = VARDONEA($<fl>2,*$2,NULL,NULL);
-			  $$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
-	|	varRefBase '=' expr ';'			{ $$ = new AstAssign($2,$1,$3); }
-	|	';'					{ $$ = NULL; }
-	//UNSUP: List of initializations
+			  $$->addNext(new AstAssign($3, new AstVarRef($3,*$2,true), $4));}
+	//			// IEEE-2012:
+	|	yVAR data_type idAny/*new*/ '=' expr
+			{ VARRESET_NONLIST(VAR); VARDTYPE($2);
+			  $$ = VARDONEA($<fl>3,*$3,NULL,NULL);
+			  $$->addNext(new AstAssign($4, new AstVarRef($4,*$3,true), $5));}
+	//			// IEEE: variable_assignment
+	|	varRefBase '=' expr			{ $$ = new AstAssign($2, $1, $3); }
 	;
 
 for_stepE<nodep>:		// IEEE: for_step + empty
@@ -2662,8 +2678,8 @@ for_stepE<nodep>:		// IEEE: for_step + empty
 	;
 
 for_step<nodep>:		// IEEE: for_step
-	//UNSUP: List of steps, instead we keep it simple
 		genvar_iteration			{ $$ = $1; }
+	|	for_step ',' genvar_iteration		{ $$ = $1; $<fl>1->v3error("Unsupported: for loop step after the first comma"); }
 	;
 
 loop_variables<nodep>:		// IEEE: loop_variables
diff --git a/test_regress/t/t_for_comma_bad.out b/test_regress/t/t_for_comma_bad.out
new file mode 100644
index 000000000..b3cb3e089
--- /dev/null
+++ b/test_regress/t/t_for_comma_bad.out
@@ -0,0 +1,10 @@
+%Error: t/t_for_comma_bad.v:13: Unsupported: for loop step after the first comma
+%Error: t/t_for_comma_bad.v:16: Unsupported: for loop step after the first comma
+%Error: t/t_for_comma_bad.v:19: Unsupported: for loop step after the first comma
+%Error: t/t_for_comma_bad.v:22: Unsupported: for loop step after the first comma
+%Error: t/t_for_comma_bad.v:25: Unsupported: for loop step after the first comma
+%Error: t/t_for_comma_bad.v:26: Unsupported: for loop initialization after the first comma
+%Error: t/t_for_comma_bad.v:27: Unsupported: for loop initialization after the first comma
+%Error: t/t_for_comma_bad.v:28: Unsupported: for loop initialization after the first comma
+%Error: t/t_for_comma_bad.v:28: Unsupported: for loop step after the first comma
+%Error: Exiting due to
diff --git a/test_regress/t/t_for_comma_bad.pl b/test_regress/t/t_for_comma_bad.pl
new file mode 100755
index 000000000..d0dce49e3
--- /dev/null
+++ b/test_regress/t/t_for_comma_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 'vlt');
+
+compile(
+    v_flags2 => ["--lint-only"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_for_comma_bad.v b/test_regress/t/t_for_comma_bad.v
new file mode 100644
index 000000000..3fec79887
--- /dev/null
+++ b/test_regress/t/t_for_comma_bad.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   integer a, b;
+
+   initial begin
+      for (; ; ) ;
+      for (; ; a=a+1) ;
+      for (; ; a=a+1, b=b+1) ;
+      for (; a<1; ) ;
+      for (; a<1; a=a+1) ;
+      for (; a<1; a=a+1, b=b+1) ;
+      for (a=0; a<1; ) ;
+      for (a=0; a<1; a=a+1) ;
+      for (a=0; a<1; a=a+1, b=b+1) ;
+      for (integer a=0; a<1; ) ;
+      for (integer a=0; a<1; a=a+1) ;
+      for (integer a=0; a<1; a=a+1, b=b+1) ;
+      for (var integer a=0; a<1; ) ;
+      for (var integer a=0; a<1; a=a+1) ;
+      for (var integer a=0; a<1; a=a+1, b=b+1) ;
+      for (integer a=0, integer b=0; a<1; ) ;
+      for (integer a=0, integer b=0; a<1; a=a+1) ;
+      for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule