Add parameters into trace files, bug706.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Support case inside, bug708. [Jan Egil Ruud]
 
+***   Add parameters into trace files, bug706. [Alex Solomatnikov]
+
 ****  Fix array bound checks on real variables.
 
 ****  Fix --skip-identical mis-detecting on OS-X, bug707.

src/V3Dead.cpp

@@ -223,7 +223,9 @@ private:
     bool mightElim(AstVar* nodep) {
 	return (!nodep->isSigPublic()	// Can't elim publics!
 		&& !nodep->isIO()
-		&& (nodep->isTemp() || nodep->isParam() || m_elimUserVars));
+		&& (nodep->isTemp()
+		    || (nodep->isParam() && !nodep->isTrace())
+		    || m_elimUserVars));  // Post-Trace can kill most anything
     }
     void deadCheckVar() {
 	// Delete any unused varscopes

src/V3TraceDecl.cpp

@@ -147,7 +147,8 @@ private:
     }
     virtual void visit(AstVarScope* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	if (!nodep->varp()->isTemp() && !nodep->varp()->isParam() && !nodep->varp()->isFuncLocal()) {
+	// Avoid updating this if (), instead see varp->isTrace()
+	if (!nodep->varp()->isTemp() && !nodep->varp()->isFuncLocal()) {
 	    UINFO(5, "    vsc "<<nodep<<endl);
 	    AstVar* varp = nodep->varp();
 	    AstScope* scopep = nodep->scopep();

src/verilog.y

@@ -3727,7 +3727,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, string name, AstRange
     // We need to autosize parameters and integers separately
     //
     // Propagate from current module tracing state
-    if (nodep->isGenVar() || nodep->isParam()) nodep->trace(false);
+    if (nodep->isGenVar()) nodep->trace(false);
     else nodep->trace(v3Global.opt.trace() && nodep->fileline()->tracingOn());
 
     // Remember the last variable created, so we can attach attributes to it in later parsing

test_regress/t/t_trace_complex.out

@@ -1,5 +1,5 @@
 $version Generated by VerilatedVcd $end
-$date Sat Dec 14 19:07:34 2013
+$date Sat Mar  8 15:28:02 2014
  $end
 $timescale 1ns $end
 
@@ -24,6 +24,12 @@ $timescale 1ns $end
    $var wire  2 $ v_strp [1:0] $end
    $var wire  4 % v_strp_strp [3:0] $end
    $var wire  2 & v_unip_strp [1:0] $end
+   $scope module p2 $end
+    $var wire 32 7 P [31:0] $end
+   $upscope $end
+   $scope module p3 $end
+    $var wire 32 8 P [31:0] $end
+   $upscope $end
    $scope module unnamedblk1 $end
     $var wire 32 . b [31:0] $end
     $scope module unnamedblk2 $end
@@ -56,6 +62,8 @@ b00000000000000000000000000000000 /
 04
 05
 06
+b00000000000000000000000000000010 7
+b00000000000000000000000000000011 8
 #10
 b00000000000000000000000000000001 #
 b11 $

test_regress/t/t_trace_complex.v

@@ -43,6 +43,9 @@ module t (clk);
    arru_arrp_t	v_arru_arrp;
    arru_strp_t	v_arru_strp;
 
+   p #(.P(2)) p2 ();
+   p #(.P(3)) p3 ();
+
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       v_strp <= ~v_strp;
@@ -65,3 +68,7 @@ module t (clk);
       end
    end
 endmodule
+
+module p;
+   parameter P = 1;
+endmodule

test_regress/t/t_trace_complex_structs.out

@@ -1,5 +1,5 @@
 $version Generated by VerilatedVcd $end
-$date Sat Dec 14 18:56:47 2013
+$date Sat Mar  8 15:28:22 2014
  $end
 $timescale 1ns $end
 
@@ -19,6 +19,12 @@ $timescale 1ns $end
    $var wire  1 ? v_arru_arru(3)(2) $end
    $var wire  1 @ v_arru_arru(4)(1) $end
    $var wire  1 A v_arru_arru(4)(2) $end
+   $scope module p2 $end
+    $var wire 32 B P [31:0] $end
+   $upscope $end
+   $scope module p3 $end
+    $var wire 32 C P [31:0] $end
+   $upscope $end
    $scope module unnamedblk1 $end
     $var wire 32 9 b [31:0] $end
     $scope module unnamedblk2 $end
@@ -102,6 +108,8 @@ b00000000000000000000000000000000 :
 0?
 0@
 0A
+b00000000000000000000000000000010 B
+b00000000000000000000000000000011 C
 #10
 b00000000000000000000000000000001 #
 1$