forked from github/verilator
Ignore %l in , bug983.
This commit is contained in:
parent
4f269e336d
commit
4475060268
2
Changes
2
Changes
@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
|
||||
|
||||
**** Add VerilatedScopeNameMap for introspection, bug966. [Todd Strader]
|
||||
|
||||
**** Ignore %l in $display, bug983. [Todd Strader]
|
||||
|
||||
**** Fix very long module names, bug937. [Todd Strader]
|
||||
|
||||
**** Fix internal error on dotted refs into generates, bug958. [Jie Xu]
|
||||
|
@ -1846,6 +1846,7 @@ private:
|
||||
switch (tolower(ch)) {
|
||||
case '%': break; // %% - just output a %
|
||||
case 'm': break; // %m - auto insert "name"
|
||||
case 'l': break; // %m - auto insert "library"
|
||||
default: // Most operators, just move to next argument
|
||||
if (argp) {
|
||||
AstNode* nextp=argp->nextp();
|
||||
|
@ -1358,9 +1358,13 @@ void EmitCStmts::displayNode(AstNode* nodep, AstScopeName* scopenamep,
|
||||
emitDispState.pushFormat(suffix);
|
||||
break;
|
||||
}
|
||||
case 'l': {
|
||||
// Better than not compiling
|
||||
emitDispState.pushFormat("----");
|
||||
break;
|
||||
}
|
||||
case 'u':
|
||||
case 'z':
|
||||
case 'l':
|
||||
case 'v':
|
||||
nodep->v3error("Unsupported: $display-like format code: %"<<pos[0]);
|
||||
break;
|
||||
|
@ -273,6 +273,9 @@ private:
|
||||
case 'm': // %m - auto insert "name"
|
||||
if (isScan) nodep->v3error("Unsupported: %m in $fscanf");
|
||||
break;
|
||||
case 'l': // %l - auto insert "library"
|
||||
if (isScan) nodep->v3error("Unsupported: %l in $fscanf");
|
||||
break;
|
||||
default: // Most operators, just move to next argument
|
||||
if (!V3Number::displayedFmtLegal(ch)) {
|
||||
nodep->v3error("Unknown $display-like format code: %"<<ch);
|
||||
|
@ -1908,6 +1908,7 @@ private:
|
||||
switch (tolower(ch)) {
|
||||
case '%': break; // %% - just output a %
|
||||
case 'm': break; // %m - auto insert "name"
|
||||
case 'l': break; // %m - auto insert "library"
|
||||
case 'd': { // Convert decimal to either 'd' or 'u'
|
||||
if (argp && argp->isSigned()) { // Convert it
|
||||
ch = '~';
|
||||
|
18
test_regress/t/t_display_l.pl
Executable file
18
test_regress/t/t_display_l.pl
Executable file
@ -0,0 +1,18 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
compile (
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
15
test_regress/t/t_display_l.v
Normal file
15
test_regress/t/t_display_l.v
Normal file
@ -0,0 +1,15 @@
|
||||
// DESCRIPTION: Verilator: $display() test for %l
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Todd Strader.
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
initial begin
|
||||
assert (0 == 0) else $fatal(2, "%l %m : %d", 0);
|
||||
$display("%l %m");
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
Loading…
Reference in New Issue
Block a user