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Tristate: Major rework to support Z tieoffs, bug499, bug510.

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This commit is contained in:
Wilson Snyder 2012-05-08 21:53:22 -04:00
parent b31a7cdcbf
commit 435a27b66a
4 changed files with 851 additions and 359 deletions
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1062
src/V3Tristate.cpp
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16
test_regress/t/t_tri_select_unsized.pl Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# Compile only test
compile (
verilator_flags2 => ["-Wno-WIDTH"],
);
ok(1);
1;

27
test_regress/t/t_tri_select_unsized.v Normal file
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@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Test of selection with unsized Z.
//
// Test selecting Z when size is not explicit. Issue 510.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [1:0] b;
wire [1:0] c;
wire [0:0] d; // Explicit width due to issue 508
wire [0:0] e;
// This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It
// does require the tri-state Z. Since we get the same effect if b is
// dimensioned [0:0], this may be connected to issue 508.
assign b[1:0] = clk ? 2'bx : 'bz;
assign c[1:0] = clk ? 2'bz : 'bx;
assign d = clk ? 1'bx : 'bz;
assign e = clk ? 1'bz : 'bx;
endmodule // t

105
test_regress/t/t_tri_unconn.v
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@ -16,39 +16,52 @@ module t (/*AUTOARG*/
wire z1 = 'z;
wire z2 = 'z;
wire z3 = 'z;
wire tog = cyc[0];
// verilator lint_off PINMISSING
t_tri0 tri0a (); // Error/warning
t_tri0 tri0b (.tn());
t_tri0 tri0z (.tn(z0));
t_tri0 #(.EXPECT(1'b0)) tri0c (.tn(1'b0));
t_tri0 #(.EXPECT(1'b1)) tri0d (.tn(1'b1)); // Warning would be reasonable given tri0 connect
t_tri0 #(.EXPECT(1'b0)) tri0e (.tn(~one));
t_tri0 #(.EXPECT(1'b1)) tri0f (.tn(one));
t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0));
t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect
t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri1 tri1a ();
t_tri1 tri1b (.tn());
t_tri1 tri1z (.tn(z1));
t_tri1 #(.EXPECT(1'b0)) tri1c (.tn(1'b0)); // Warning would be reasonable given tri1 connect
t_tri1 #(.EXPECT(1'b1)) tri1d (.tn(1'b1));
t_tri1 #(.EXPECT(1'b0)) tri1e (.tn(~one));
t_tri1 #(.EXPECT(1'b1)) tri1f (.tn(one));
t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1));
t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect
t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri2 tri2a ();
t_tri2 tri2b (.tn());
t_tri2 tri2z (.tn(z2));
t_tri2 #(.EXPECT(1'b0)) tri2c (.tn(1'b0));
t_tri2 #(.EXPECT(1'b1)) tri2d (.tn(1'b1));
t_tri2 #(.EXPECT(1'b0)) tri2e (.tn(~one));
t_tri2 #(.EXPECT(1'b1)) tri2f (.tn(one));
t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2));
t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri3 tri3a ();
t_tri3 tri3b (.tn());
t_tri3 tri3z (.tn(z3));
t_tri3 #(.EXPECT(1'b0)) tri3c (.tn(1'b0));
t_tri3 #(.EXPECT(1'b1)) tri3d (.tn(1'b1));
t_tri3 #(.EXPECT(1'b0)) tri3e (.tn(~one));
t_tri3 #(.EXPECT(1'b1)) tri3f (.tn(one));
t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3));
t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
// verilator lint_on PINMISSING
// Test loop
@ -63,37 +76,49 @@ module t (/*AUTOARG*/
endmodule
module t_tri0
#(parameter EXPECT=1'b0)
(tn);
(line, expval, tn);
input integer line;
input expval;
input tn; // Illegal to be inout; spec requires net connection to any inout
tri0 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== EXPECT) $stop;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri1
#(parameter EXPECT=1'b1)
(tn);
(line, expval, tn);
input integer line;
input expval;
input tn;
tri1 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== EXPECT) $stop;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri2
#(parameter EXPECT=1'b0)
(tn);
(line, expval, tn);
input integer line;
input expval;
input tn;
pulldown(tn);
wire clk = t.clk;
always @(posedge clk) if (tn !== EXPECT) $stop;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri3
#(parameter EXPECT=1'b1)
(tn);
(line, expval, tn);
input integer line;
input expval;
input tn;
pullup(tn);
wire clk = t.clk;
always @(posedge clk) if (tn !== EXPECT) $stop;
always @(negedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule