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Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.

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This commit is contained in:
Wilson Snyder 2022-01-17 16:22:07 -05:00
parent 21e05c43dd
commit 434c3c3ef3
29 changed files with 1420 additions and 1428 deletions
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1
Changes
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@ -14,6 +14,7 @@ Verilator 4.219 devel
**Minor:**
* Removed the deprecated lint_off flag -msg; use -rule instead.
* Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
Verilator 4.218 2022-01-17

4
docs/guide/deprecations.rst
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@ -16,10 +16,6 @@ Verilated_heavy.h
"verilated.h". Verilated_heavy.h is planned for removal no sooner than
July 2022.
XML locations
The XML "fl" attribute has been replaced with the "loc" attribute. "fl"
is planned for removal no sooner than January 2021.
Option `--cdc`
The experimental `--cdc` option is believed to be generally unused and is
planned for removeal no sooner than January 2023.

3
docs/xml.rst
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@ -46,9 +46,6 @@ The XML document consists of 4 sections within the top level
hierarchy. Each instance is represented with the ``<cell>`` element
with the following attributes:
- ``fl`` (deprecated): The file id and line number where the module
was instanced. Use ``loc`` instead.
- ``loc``: The file id, first line number, last line number, first
column number and last column number of the identifier where the
module was instanced, separated by commas.

9
src/V3EmitXml.cpp
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@ -61,7 +61,7 @@ class EmitXmlFileVisitor final : public VNVisitor {
void outputTag(AstNode* nodep, const string& tagin) {
string tag = tagin;
if (tag == "") tag = VString::downcase(nodep->typeName());
puts("<" + tag + " " + nodep->fileline()->xml());
puts("<" + tag);
puts(" " + nodep->fileline()->xmlDetailedLocation());
if (VN_IS(nodep, NodeDType)) {
puts(" id=");
@ -386,8 +386,7 @@ private:
if (nodep->level() >= 0
&& nodep->level() <= 2) { // ==2 because we don't add wrapper when in XML mode
m_os << "<cells>\n";
m_os << "<cell " << nodep->fileline()->xml() << " "
<< nodep->fileline()->xmlDetailedLocation() //
m_os << "<cell " << nodep->fileline()->xmlDetailedLocation() //
<< " name=\"" << nodep->prettyName() << "\""
<< " submodname=\"" << nodep->prettyName() << "\""
<< " hier=\"" << nodep->prettyName() << "\"";
@ -405,8 +404,8 @@ private:
virtual void visit(AstCell* nodep) override {
if (nodep->modp()->dead()) return;
if (!m_hasChildren) m_os << ">\n";
m_os << "<cell " << nodep->fileline()->xml() << " "
<< nodep->fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() << "\""
m_os << "<cell " << nodep->fileline()->xmlDetailedLocation() << " name=\"" << nodep->name()
<< "\""
<< " submodname=\"" << nodep->modName() << "\""
<< " hier=\"" << m_hier + nodep->name() << "\"";
const std::string hier = m_hier;

1
src/V3FileLine.h
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@ -200,7 +200,6 @@ public:
string filebasenameNoExt() const;
string firstColumnLetters() const;
string profileFuncname() const;
string xml() const { return "fl=\"" + filenameLetters() + cvtToStr(lastLineno()) + "\""; }
string xmlDetailedLocation() const;
string lineDirectiveStrg(int enterExit) const;

6
test_regress/t/t_clk_concat.pl
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@ -17,9 +17,9 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="d74" loc=".*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d75" loc=".*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d76" loc=".*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,74,.*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,75,.*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,76,.*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
}
execute(

8
test_regress/t/t_clk_concat_vlt.pl
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@ -18,10 +18,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e78" loc=".*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e79" loc=".*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e80" loc=".*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e82" loc=".*?" name="data_in" .*dir="input" .*vartype="logic" origName="data_in" clocker="false" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,78,.*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,79,.*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,80,.*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,82,.*?" name="data_in" .*dir="input" .*vartype="logic" origName="data_in" clocker="false" public="true"\/\>/i);
}
execute(

2
test_regress/t/t_dedupe_clk_gate.pl
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@ -17,7 +17,7 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e44" loc=".*?" name="t.f0.clock_gate.clken_latched" dtype_id="1" vartype="logic" origName="clken_latched" clock_enable="true" latched="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,44,.*?" name="t.f0.clock_gate.clken_latched" dtype_id="1" vartype="logic" origName="clken_latched" clock_enable="true" latched="true"\/\>/i);
file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4);
}

8
test_regress/t/t_dpi_var.pl
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@ -18,10 +18,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="d56" loc=".*?" name="formatted" dtype_id="\d+" dir="input" vartype="string" origName="formatted" sformat="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d77" loc=".*?" name="t.sub.in" dtype_id="\d+" vartype="int" origName="in" public="true" public_flat_rd="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d78" loc=".*?" name="t.sub.fr_a" dtype_id="\d+" vartype="int" origName="fr_a" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d79" loc=".*?" name="t.sub.fr_b" dtype_id="\d+" vartype="int" origName="fr_b" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,56,.*?" name="formatted" dtype_id="\d+" dir="input" vartype="string" origName="formatted" sformat="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,77,.*?" name="t.sub.in" dtype_id="\d+" vartype="int" origName="in" public="true" public_flat_rd="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,78,.*?" name="t.sub.fr_a" dtype_id="\d+" vartype="int" origName="fr_a" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,79,.*?" name="t.sub.fr_b" dtype_id="\d+" vartype="int" origName="fr_b" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
}
execute(

8
test_regress/t/t_dpi_var_vlt.pl
View File

@ -20,10 +20,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e58" loc=".*?" name="formatted" dtype_id="\d+" dir="input" vartype="string" origName="formatted" sformat="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e81" loc=".*?" name="t.sub.in" dtype_id="\d+" vartype="int" origName="in" public="true" public_flat_rd="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e82" loc=".*?" name="t.sub.fr_a" dtype_id="\d+" vartype="int" origName="fr_a" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e83" loc=".*?" name="t.sub.fr_b" dtype_id="\d+" vartype="int" origName="fr_b" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,58,.*?" name="formatted" dtype_id="\d+" dir="input" vartype="string" origName="formatted" sformat="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,81,.*?" name="t.sub.in" dtype_id="\d+" vartype="int" origName="in" public="true" public_flat_rd="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,82,.*?" name="t.sub.fr_a" dtype_id="\d+" vartype="int" origName="fr_a" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,83,.*?" name="t.sub.fr_b" dtype_id="\d+" vartype="int" origName="fr_b" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
}
execute(

8
test_regress/t/t_func_dotted_inl0.pl
View File

@ -18,10 +18,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<module fl="d84" loc=".*?" name="ma" origName="ma" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="d99" loc=".*?" name="mb" origName="mb" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="d127" loc=".*?" name="mc" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="d127" loc=".*?" name="mc__PB1" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="d,84,.*?" name="ma" origName="ma" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="d,99,.*?" name="mb" origName="mb" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="d,127,.*?" name="mc" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="d,127,.*?" name="mc__PB1" origName="mc" public="true"\>/i);
}
execute(

8
test_regress/t/t_func_dotted_inl0_vlt.pl
View File

@ -18,10 +18,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<module fl="e84" loc=".*?" name="ma" origName="ma" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="e99" loc=".*?" name="mb" origName="mb" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="e127" loc=".*?" name="mc" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module fl="e127" loc=".*?" name="mc__PB1" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="e,84,.*?" name="ma" origName="ma" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="e,99,.*?" name="mb" origName="mb" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="e,127,.*?" name="mc" origName="mc" public="true"\>/i);
file_grep("$out_filename", qr/\<module loc="e,127,.*?" name="mc__PB1" origName="mc" public="true"\>/i);
}
execute(

4
test_regress/t/t_func_dotted_inl2.pl
View File

@ -18,8 +18,8 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<instance fl="d87" loc=".*?" name="t.ma0.mb0" defName="mb" origName="mb0"\/\>/i);
file_grep("$out_filename", qr/\<module fl="d99" loc=".*?" name="mb" origName="mb"\>/i);
file_grep("$out_filename", qr/\<instance loc="d,87,.*?" name="t.ma0.mb0" defName="mb" origName="mb0"\/\>/i);
file_grep("$out_filename", qr/\<module loc="d,99,.*?" name="mb" origName="mb"\>/i);
}
execute(

4
test_regress/t/t_func_dotted_inl2_vlt.pl
View File

@ -18,8 +18,8 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<instance fl="e87" loc=".*?" name="t.ma0.mb0" defName="mb" origName="mb0"\/\>/i);
file_grep("$out_filename", qr/\<module fl="e99" loc=".*?" name="mb" origName="mb"\>/i);
file_grep("$out_filename", qr/\<instance loc="e,87,.*?" name="t.ma0.mb0" defName="mb" origName="mb0"\/\>/i);
file_grep("$out_filename", qr/\<module loc="e,99,.*?" name="mb" origName="mb"\>/i);
}
execute(

12
test_regress/t/t_inst_tree_inl0_pub0.pl
View File

@ -18,12 +18,12 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<module fl="e56" loc=".*?" name="l1" origName="l1"\>/i);
file_grep("$out_filename", qr/\<module fl="e62" loc=".*?" name="l2" origName="l2"\>/i);
file_grep("$out_filename", qr/\<module fl="e69" loc=".*?" name="l3" origName="l3"\>/i);
file_grep("$out_filename", qr/\<module fl="e76" loc=".*?" name="l4" origName="l4"\>/i);
file_grep("$out_filename", qr/\<module fl="e83" loc=".*?" name="l5__P2" origName="l5"\>/i);
file_grep("$out_filename", qr/\<module fl="e83" loc=".*?" name="l5__P1" origName="l5"\>/i);
file_grep("$out_filename", qr/\<module loc="e,56,.*?" name="l1" origName="l1"\>/i);
file_grep("$out_filename", qr/\<module loc="e,62,.*?" name="l2" origName="l2"\>/i);
file_grep("$out_filename", qr/\<module loc="e,69,.*?" name="l3" origName="l3"\>/i);
file_grep("$out_filename", qr/\<module loc="e,76,.*?" name="l4" origName="l4"\>/i);
file_grep("$out_filename", qr/\<module loc="e,83,.*?" name="l5__P2" origName="l5"\>/i);
file_grep("$out_filename", qr/\<module loc="e,83,.*?" name="l5__P1" origName="l5"\>/i);
}
execute(

6
test_regress/t/t_inst_tree_inl1_pub0.pl
View File

@ -18,9 +18,9 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e70" loc=".*?" name="t.u.u0.u0.z1" dtype_id="\d+" vartype="logic" origName="z1"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e70" loc=".*?" name="t.u.u0.u1.z1" dtype_id="\d+" vartype="logic" origName="z1"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e70" loc=".*?" name="t.u.u1.u0.z0" dtype_id="\d+" vartype="logic" origName="z0"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,70,.*?" name="t.u.u0.u0.z1" dtype_id="\d+" vartype="logic" origName="z1"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,70,.*?" name="t.u.u0.u1.z1" dtype_id="\d+" vartype="logic" origName="z1"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,70,.*?" name="t.u.u1.u0.z0" dtype_id="\d+" vartype="logic" origName="z0"\/\>/i);
}
execute(

6
test_regress/t/t_inst_tree_inl1_pub1.pl
View File

@ -19,9 +19,9 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e70" loc=".*?" name="u.u0.u0.z0" dtype_id="\d+" vartype="logic" origName="z0" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e85" loc=".*?" name="u.u0.u0.u0.u0.z1" dtype_id="\d+" vartype="logic" origName="z1" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e83" loc=".*?" name="u.u0.u1.u0.u0.z" dtype_id="\d+" vartype="logic" origName="z" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,70,.*?" name="u.u0.u0.z0" dtype_id="\d+" vartype="logic" origName="z0" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,85,.*?" name="u.u0.u0.u0.u0.z1" dtype_id="\d+" vartype="logic" origName="z1" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,83,.*?" name="u.u0.u1.u0.u0.z" dtype_id="\d+" vartype="logic" origName="z" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
}
execute(

2
test_regress/t/t_trace_public_sig_vlt.pl
View File

@ -22,7 +22,7 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e47" loc=".*?" name="GSR" dtype_id="1" vartype="logic" origName="GSR" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,47,.*?" name="GSR" dtype_id="1" vartype="logic" origName="GSR" public="true" public_flat_rd="true" public_flat_rw="true"\/\>/i);
}
execute(

10
test_regress/t/t_unopt_combo_isolate.pl
View File

@ -19,11 +19,11 @@ compile(
if ($Self->{vlt_all}) {
file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i);
file_grep("$out_filename", qr/\<var fl="d23" loc=".*?" name="t.b" dtype_id="\d+" vartype="logic" origName="b" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d99" loc=".*?" name="__Vfunc_t.file.get_31_16__0__Vfuncout" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d100" loc=".*?" name="__Vfunc_t.file.get_31_16__0__t_crc" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d112" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_crc" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d113" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_c" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_c" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,23,.*?" name="t.b" dtype_id="\d+" vartype="logic" origName="b" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,99,.*?" name="__Vfunc_t.file.get_31_16__0__Vfuncout" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,100,.*?" name="__Vfunc_t.file.get_31_16__0__t_crc" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,112,.*?" name="__Vtask_t.file.set_b_d__1__t_crc" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="d,113,.*?" name="__Vtask_t.file.set_b_d__1__t_c" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_c" isolate_assignments="true"\/\>/i);
}
execute(

10
test_regress/t/t_unopt_combo_isolate_vlt.pl
View File

@ -19,11 +19,11 @@ compile(
if ($Self->{vlt_all}) {
file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i);
file_grep("$out_filename", qr/\<var fl="e23" loc=".*?" name="t.b" dtype_id="\d+" vartype="logic" origName="b" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e104" loc=".*?" name="__Vfunc_t.file.get_31_16__0__Vfuncout" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e105" loc=".*?" name="__Vfunc_t.file.get_31_16__0__t_crc" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e115" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_crc" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e116" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_c" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_c" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,23,.*?" name="t.b" dtype_id="\d+" vartype="logic" origName="b" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,104,.*?" name="__Vfunc_t.file.get_31_16__0__Vfuncout" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,105,.*?" name="__Vfunc_t.file.get_31_16__0__t_crc" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,115,.*?" name="__Vtask_t.file.set_b_d__1__t_crc" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc" isolate_assignments="true"\/\>/i);
file_grep("$out_filename", qr/\<var loc="e,116,.*?" name="__Vtask_t.file.set_b_d__1__t_c" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_c" isolate_assignments="true"\/\>/i);
}
execute(

128
test_regress/t/t_var_port_xml.out
View File

@ -11,119 +11,119 @@
<file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d18" loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>
<cell loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>
</cells>
<cells>
<cell fl="d24" loc="d,24,8,24,11" name="mh5" submodname="mh5" hier="mh5"/>
<cell loc="d,24,8,24,11" name="mh5" submodname="mh5" hier="mh5"/>
</cells>
<cells>
<cell fl="d26" loc="d,26,8,26,11" name="mh6" submodname="mh6" hier="mh6"/>
<cell loc="d,26,8,26,11" name="mh6" submodname="mh6" hier="mh6"/>
</cells>
<cells>
<cell fl="d28" loc="d,28,8,28,11" name="mh7" submodname="mh7" hier="mh7"/>
<cell loc="d,28,8,28,11" name="mh7" submodname="mh7" hier="mh7"/>
</cells>
<cells>
<cell fl="d30" loc="d,30,8,30,11" name="mh8" submodname="mh8" hier="mh8"/>
<cell loc="d,30,8,30,11" name="mh8" submodname="mh8" hier="mh8"/>
</cells>
<cells>
<cell fl="d32" loc="d,32,8,32,11" name="mh9" submodname="mh9" hier="mh9"/>
<cell loc="d,32,8,32,11" name="mh9" submodname="mh9" hier="mh9"/>
</cells>
<cells>
<cell fl="d34" loc="d,34,8,34,12" name="mh10" submodname="mh10" hier="mh10"/>
<cell loc="d,34,8,34,12" name="mh10" submodname="mh10" hier="mh10"/>
</cells>
<cells>
<cell fl="d36" loc="d,36,8,36,12" name="mh11" submodname="mh11" hier="mh11"/>
<cell loc="d,36,8,36,12" name="mh11" submodname="mh11" hier="mh11"/>
</cells>
<cells>
<cell fl="d38" loc="d,38,8,38,12" name="mh12" submodname="mh12" hier="mh12"/>
<cell loc="d,38,8,38,12" name="mh12" submodname="mh12" hier="mh12"/>
</cells>
<cells>
<cell fl="d40" loc="d,40,8,40,12" name="mh13" submodname="mh13" hier="mh13"/>
<cell loc="d,40,8,40,12" name="mh13" submodname="mh13" hier="mh13"/>
</cells>
<cells>
<cell fl="d50" loc="d,50,8,50,12" name="mh17" submodname="mh17" hier="mh17"/>
<cell loc="d,50,8,50,12" name="mh17" submodname="mh17" hier="mh17"/>
</cells>
<cells>
<cell fl="d52" loc="d,52,8,52,12" name="mh18" submodname="mh18" hier="mh18"/>
<cell loc="d,52,8,52,12" name="mh18" submodname="mh18" hier="mh18"/>
</cells>
<cells>
<cell fl="d54" loc="d,54,8,54,12" name="mh19" submodname="mh19" hier="mh19"/>
<cell loc="d,54,8,54,12" name="mh19" submodname="mh19" hier="mh19"/>
</cells>
<cells>
<cell fl="d56" loc="d,56,8,56,12" name="mh20" submodname="mh20" hier="mh20"/>
<cell loc="d,56,8,56,12" name="mh20" submodname="mh20" hier="mh20"/>
</cells>
<cells>
<cell fl="d58" loc="d,58,8,58,12" name="mh21" submodname="mh21" hier="mh21"/>
<cell loc="d,58,8,58,12" name="mh21" submodname="mh21" hier="mh21"/>
</cells>
<netlist>
<module fl="d18" loc="d,18,8,18,11" name="mh2" origName="mh2">
<var fl="d18" loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer"/>
<module loc="d,18,8,18,11" name="mh2" origName="mh2">
<var loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer"/>
</module>
<module fl="d24" loc="d,24,8,24,11" name="mh5" origName="mh5">
<var fl="d24" loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic"/>
<module loc="d,24,8,24,11" name="mh5" origName="mh5">
<var loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic"/>
</module>
<module fl="d26" loc="d,26,8,26,11" name="mh6" origName="mh6">
<var fl="d26" loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic"/>
<module loc="d,26,8,26,11" name="mh6" origName="mh6">
<var loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic"/>
</module>
<module fl="d28" loc="d,28,8,28,11" name="mh7" origName="mh7">
<var fl="d28" loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
<module loc="d,28,8,28,11" name="mh7" origName="mh7">
<var loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
</module>
<module fl="d30" loc="d,30,8,30,11" name="mh8" origName="mh8">
<var fl="d30" loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic"/>
<module loc="d,30,8,30,11" name="mh8" origName="mh8">
<var loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic"/>
</module>
<module fl="d32" loc="d,32,8,32,11" name="mh9" origName="mh9">
<var fl="d32" loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
<module loc="d,32,8,32,11" name="mh9" origName="mh9">
<var loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
</module>
<module fl="d34" loc="d,34,8,34,12" name="mh10" origName="mh10">
<var fl="d34" loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<module loc="d,34,8,34,12" name="mh10" origName="mh10">
<var loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
</module>
<module fl="d36" loc="d,36,8,36,12" name="mh11" origName="mh11">
<var fl="d36" loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer"/>
<module loc="d,36,8,36,12" name="mh11" origName="mh11">
<var loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer"/>
</module>
<module fl="d38" loc="d,38,8,38,12" name="mh12" origName="mh12">
<var fl="d38" loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6"/>
<module loc="d,38,8,38,12" name="mh12" origName="mh12">
<var loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6"/>
</module>
<module fl="d40" loc="d,40,8,40,12" name="mh13" origName="mh13">
<var fl="d40" loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6"/>
<module loc="d,40,8,40,12" name="mh13" origName="mh13">
<var loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6"/>
</module>
<module fl="d50" loc="d,50,8,50,12" name="mh17" origName="mh17">
<var fl="d50" loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
<var fl="d50" loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
<module loc="d,50,8,50,12" name="mh17" origName="mh17">
<var loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
<var loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
</module>
<module fl="d52" loc="d,52,8,52,12" name="mh18" origName="mh18">
<var fl="d52" loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
<var fl="d52" loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
<module loc="d,52,8,52,12" name="mh18" origName="mh18">
<var loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
<var loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
</module>
<module fl="d54" loc="d,54,8,54,12" name="mh19" origName="mh19">
<var fl="d54" loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<var fl="d54" loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer"/>
<module loc="d,54,8,54,12" name="mh19" origName="mh19">
<var loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<var loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer"/>
</module>
<module fl="d56" loc="d,56,8,56,12" name="mh20" origName="mh20">
<var fl="d56" loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6"/>
<var fl="d56" loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6"/>
<module loc="d,56,8,56,12" name="mh20" origName="mh20">
<var loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6"/>
<var loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6"/>
</module>
<module fl="d58" loc="d,58,8,58,12" name="mh21" origName="mh21">
<var fl="d58" loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6"/>
<var fl="d58" loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic"/>
<module loc="d,58,8,58,12" name="mh21" origName="mh21">
<var loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6"/>
<var loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic"/>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<unpackarraydtype fl="d58" loc="d,58,34,58,35" id="6" sub_dtype_id="2">
<range fl="d58" loc="d,58,34,58,35">
<const fl="d58" loc="d,58,35,58,36" name="32&apos;sh5" dtype_id="7"/>
<const fl="d58" loc="d,58,37,58,38" name="32&apos;sh0" dtype_id="7"/>
<typetable loc="a,0,0,0,0">
<unpackarraydtype loc="d,58,34,58,35" id="6" sub_dtype_id="2">
<range loc="d,58,34,58,35">
<const loc="d,58,35,58,36" name="32&apos;sh5" dtype_id="7"/>
<const loc="d,58,37,58,38" name="32&apos;sh0" dtype_id="7"/>
</range>
</unpackarraydtype>
<basicdtype fl="d58" loc="d,58,41,58,56" id="2" name="logic"/>
<unpackarraydtype fl="d40" loc="d,40,36,40,37" id="5" sub_dtype_id="2">
<range fl="d40" loc="d,40,36,40,37">
<const fl="d40" loc="d,40,37,40,38" name="32&apos;sh5" dtype_id="7"/>
<const fl="d40" loc="d,40,39,40,40" name="32&apos;sh0" dtype_id="7"/>
<basicdtype loc="d,58,41,58,56" id="2" name="logic"/>
<unpackarraydtype loc="d,40,36,40,37" id="5" sub_dtype_id="2">
<range loc="d,40,36,40,37">
<const loc="d,40,37,40,38" name="32&apos;sh5" dtype_id="7"/>
<const loc="d,40,39,40,40" name="32&apos;sh0" dtype_id="7"/>
</range>
</unpackarraydtype>
<basicdtype fl="d38" loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
<basicdtype fl="d34" loc="d,34,27,34,28" id="3" name="logic" left="5" right="0" signed="true"/>
<basicdtype fl="d18" loc="d,18,19,18,26" id="1" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d40" loc="d,40,37,40,38" id="7" name="logic" left="31" right="0" signed="true"/>
<basicdtype loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
<basicdtype loc="d,34,27,34,28" id="3" name="logic" left="5" right="0" signed="true"/>
<basicdtype loc="d,18,19,18,26" id="1" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,40,37,40,38" id="7" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

1886
test_regress/t/t_xml_debugcheck.out
View File

File diff suppressed because it is too large Load Diff

96
test_regress/t/t_xml_first.out
View File

@ -11,75 +11,75 @@
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d7" loc="d,7,8,7,9" name="t" submodname="t" hier="t">
<cell fl="d20" loc="d,20,4,20,9" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
<cell fl="d25" loc="d,25,6,25,11" name="cell2" submodname="mod2" hier="t.cell2"/>
<cell loc="d,7,8,7,9" name="t" submodname="t" hier="t">
<cell loc="d,20,4,20,9" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
<cell loc="d,25,6,25,11" name="cell2" submodname="mod2" hier="t.cell2"/>
</cell>
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q"/>
<var fl="d17" loc="d,17,22,17,29" name="between" dtype_id="2" vartype="logic" origName="between"/>
<instance fl="d20" loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port fl="d20" loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
<varref fl="d20" loc="d,20,14,20,21" name="between" dtype_id="2"/>
<module loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d"/>
<var loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q"/>
<var loc="d,17,22,17,29" name="between" dtype_id="2" vartype="logic" origName="between"/>
<instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
<varref loc="d,20,14,20,21" name="between" dtype_id="2"/>
</port>
<port fl="d21" loc="d,21,12,21,15" name="clk" direction="in" portIndex="2">
<varref fl="d21" loc="d,21,42,21,45" name="clk" dtype_id="1"/>
<port loc="d,21,12,21,15" name="clk" direction="in" portIndex="2">
<varref loc="d,21,42,21,45" name="clk" dtype_id="1"/>
</port>
<port fl="d22" loc="d,22,12,22,13" name="d" direction="in" portIndex="3">
<varref fl="d22" loc="d,22,42,22,43" name="d" dtype_id="2"/>
<port loc="d,22,12,22,13" name="d" direction="in" portIndex="3">
<varref loc="d,22,42,22,43" name="d" dtype_id="2"/>
</port>
</instance>
<instance fl="d25" loc="d,25,6,25,11" name="cell2" defName="mod2" origName="cell2">
<port fl="d25" loc="d,25,14,25,15" name="d" direction="in" portIndex="1">
<varref fl="d25" loc="d,25,16,25,23" name="between" dtype_id="2"/>
<instance loc="d,25,6,25,11" name="cell2" defName="mod2" origName="cell2">
<port loc="d,25,14,25,15" name="d" direction="in" portIndex="1">
<varref loc="d,25,16,25,23" name="between" dtype_id="2"/>
</port>
<port fl="d26" loc="d,26,14,26,15" name="q" direction="out" portIndex="2">
<varref fl="d26" loc="d,26,42,26,43" name="q" dtype_id="2"/>
<port loc="d,26,14,26,15" name="q" direction="out" portIndex="2">
<varref loc="d,26,42,26,43" name="q" dtype_id="2"/>
</port>
<port fl="d27" loc="d,27,14,27,17" name="clk" direction="in" portIndex="3">
<varref fl="d27" loc="d,27,42,27,45" name="clk" dtype_id="1"/>
<port loc="d,27,14,27,17" name="clk" direction="in" portIndex="3">
<varref loc="d,27,42,27,45" name="clk" dtype_id="1"/>
</port>
</instance>
</module>
<module fl="d31" loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
<var fl="d32" loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const fl="d19" loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
<module loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
<var loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var fl="d34" loc="d,34,24,34,27" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var fl="d35" loc="d,35,30,35,31" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var fl="d36" loc="d,36,30,36,31" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var fl="d39" loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const fl="d39" loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
<var loc="d,34,24,34,27" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<always fl="d41" loc="d,41,4,41,10">
<sentree fl="d41" loc="d,41,11,41,12">
<senitem fl="d41" loc="d,41,13,41,20" edgeType="POS">
<varref fl="d41" loc="d,41,21,41,24" name="clk" dtype_id="1"/>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="1"/>
</senitem>
</sentree>
<assigndly fl="d42" loc="d,42,8,42,10" dtype_id="2">
<varref fl="d42" loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref fl="d42" loc="d,42,6,42,7" name="q" dtype_id="2"/>
<assigndly loc="d,42,8,42,10" dtype_id="2">
<varref loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref loc="d,42,6,42,7" name="q" dtype_id="2"/>
</assigndly>
</always>
</module>
<module fl="d46" loc="d,46,8,46,12" name="mod2" origName="mod2">
<var fl="d48" loc="d,48,10,48,13" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var fl="d49" loc="d,49,16,49,17" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var fl="d50" loc="d,50,22,50,23" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign fl="d53" loc="d,53,13,53,14" dtype_id="2">
<varref fl="d53" loc="d,53,15,53,16" name="d" dtype_id="2"/>
<varref fl="d53" loc="d,53,11,53,12" name="q" dtype_id="2"/>
<module loc="d,46,8,46,12" name="mod2" origName="mod2">
<var loc="d,48,10,48,13" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign loc="d,53,13,53,14" dtype_id="2">
<varref loc="d,53,15,53,16" name="d" dtype_id="2"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="2"/>
</contassign>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d48" loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype fl="d14" loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

154
test_regress/t/t_xml_flat.out
View File

@ -11,104 +11,104 @@
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d7" loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/>
<cell loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="$root" origName="$root" topModule="1" public="true">
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var fl="d13" loc="d,13,10,13,13" name="t.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var fl="d14" loc="d,14,16,14,17" name="t.d" dtype_id="2" vartype="logic" origName="d"/>
<var fl="d15" loc="d,15,22,15,23" name="t.q" dtype_id="2" vartype="logic" origName="q"/>
<var fl="d17" loc="d,17,22,17,29" name="t.between" dtype_id="2" vartype="logic" origName="between"/>
<var fl="d32" loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const fl="d19" loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
<module loc="d,7,8,7,9" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="t.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="t.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,15,22,15,23" name="t.q" dtype_id="2" vartype="logic" origName="q"/>
<var loc="d,17,22,17,29" name="t.between" dtype_id="2" vartype="logic" origName="between"/>
<var loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var fl="d34" loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var fl="d35" loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2" vartype="logic" origName="d"/>
<var fl="d36" loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2" vartype="logic" origName="q"/>
<var fl="d39" loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const fl="d39" loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
<var loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<var fl="d48" loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var fl="d49" loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2" vartype="logic" origName="d"/>
<var fl="d50" loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2" vartype="logic" origName="q"/>
<topscope fl="d7" loc="d,7,8,7,9">
<scope fl="d7" loc="d,7,8,7,9" name="TOP">
<varscope fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varscope fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varscope fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varscope fl="d13" loc="d,13,10,13,13" name="t.clk" dtype_id="1"/>
<varscope fl="d14" loc="d,14,16,14,17" name="t.d" dtype_id="2"/>
<varscope fl="d15" loc="d,15,22,15,23" name="t.q" dtype_id="2"/>
<varscope fl="d17" loc="d,17,22,17,29" name="t.between" dtype_id="2"/>
<varscope fl="d32" loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope fl="d34" loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1"/>
<varscope fl="d35" loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2"/>
<varscope fl="d36" loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2"/>
<varscope fl="d39" loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope fl="d48" loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1"/>
<varscope fl="d49" loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2"/>
<varscope fl="d50" loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2"/>
<assignalias fl="d13" loc="d,13,10,13,13" dtype_id="1">
<varref fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varref fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<var loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2" vartype="logic" origName="q"/>
<topscope loc="d,7,8,7,9">
<scope loc="d,7,8,7,9" name="TOP">
<varscope loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varscope loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="1"/>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="2"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="2"/>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="2"/>
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1"/>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2"/>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2"/>
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1"/>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2"/>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2"/>
<assignalias loc="d,13,10,13,13" dtype_id="1">
<varref loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varref loc="d,13,10,13,13" name="clk" dtype_id="1"/>
</assignalias>
<assignalias fl="d14" loc="d,14,16,14,17" dtype_id="2">
<varref fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varref fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2"/>
<assignalias loc="d,14,16,14,17" dtype_id="2">
<varref loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varref loc="d,14,16,14,17" name="d" dtype_id="2"/>
</assignalias>
<assignalias fl="d15" loc="d,15,22,15,23" dtype_id="2">
<varref fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varref fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2"/>
<assignalias loc="d,15,22,15,23" dtype_id="2">
<varref loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varref loc="d,15,22,15,23" name="q" dtype_id="2"/>
</assignalias>
<assignalias fl="d34" loc="d,34,24,34,27" dtype_id="1">
<varref fl="d34" loc="d,34,24,34,27" name="t.clk" dtype_id="1"/>
<varref fl="d34" loc="d,34,24,34,27" name="cell1.clk" dtype_id="1"/>
<assignalias loc="d,34,24,34,27" dtype_id="1">
<varref loc="d,34,24,34,27" name="t.clk" dtype_id="1"/>
<varref loc="d,34,24,34,27" name="cell1.clk" dtype_id="1"/>
</assignalias>
<assignalias fl="d35" loc="d,35,30,35,31" dtype_id="2">
<varref fl="d35" loc="d,35,30,35,31" name="t.d" dtype_id="2"/>
<varref fl="d35" loc="d,35,30,35,31" name="cell1.d" dtype_id="2"/>
<assignalias loc="d,35,30,35,31" dtype_id="2">
<varref loc="d,35,30,35,31" name="t.d" dtype_id="2"/>
<varref loc="d,35,30,35,31" name="cell1.d" dtype_id="2"/>
</assignalias>
<assignalias fl="d36" loc="d,36,30,36,31" dtype_id="2">
<varref fl="d36" loc="d,36,30,36,31" name="t.between" dtype_id="2"/>
<varref fl="d36" loc="d,36,30,36,31" name="cell1.q" dtype_id="2"/>
<assignalias loc="d,36,30,36,31" dtype_id="2">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="2"/>
<varref loc="d,36,30,36,31" name="cell1.q" dtype_id="2"/>
</assignalias>
<always fl="d41" loc="d,41,4,41,10">
<sentree fl="d41" loc="d,41,11,41,12">
<senitem fl="d41" loc="d,41,13,41,20" edgeType="POS">
<varref fl="d41" loc="d,41,21,41,24" name="clk" dtype_id="1"/>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="1"/>
</senitem>
</sentree>
<assigndly fl="d42" loc="d,42,8,42,10" dtype_id="2">
<varref fl="d42" loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref fl="d42" loc="d,42,6,42,7" name="t.between" dtype_id="2"/>
<assigndly loc="d,42,8,42,10" dtype_id="2">
<varref loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref loc="d,42,6,42,7" name="t.between" dtype_id="2"/>
</assigndly>
</always>
<assignalias fl="d48" loc="d,48,10,48,13" dtype_id="1">
<varref fl="d48" loc="d,48,10,48,13" name="t.clk" dtype_id="1"/>
<varref fl="d48" loc="d,48,10,48,13" name="cell2.clk" dtype_id="1"/>
<assignalias loc="d,48,10,48,13" dtype_id="1">
<varref loc="d,48,10,48,13" name="t.clk" dtype_id="1"/>
<varref loc="d,48,10,48,13" name="cell2.clk" dtype_id="1"/>
</assignalias>
<assignalias fl="d49" loc="d,49,16,49,17" dtype_id="2">
<varref fl="d49" loc="d,49,16,49,17" name="t.between" dtype_id="2"/>
<varref fl="d49" loc="d,49,16,49,17" name="cell2.d" dtype_id="2"/>
<assignalias loc="d,49,16,49,17" dtype_id="2">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="2"/>
<varref loc="d,49,16,49,17" name="cell2.d" dtype_id="2"/>
</assignalias>
<assignalias fl="d50" loc="d,50,22,50,23" dtype_id="2">
<varref fl="d50" loc="d,50,22,50,23" name="t.q" dtype_id="2"/>
<varref fl="d50" loc="d,50,22,50,23" name="cell2.q" dtype_id="2"/>
<assignalias loc="d,50,22,50,23" dtype_id="2">
<varref loc="d,50,22,50,23" name="t.q" dtype_id="2"/>
<varref loc="d,50,22,50,23" name="cell2.q" dtype_id="2"/>
</assignalias>
<contassign fl="d53" loc="d,53,13,53,14" dtype_id="2">
<varref fl="d53" loc="d,53,15,53,16" name="t.between" dtype_id="2"/>
<varref fl="d53" loc="d,53,11,53,12" name="q" dtype_id="2"/>
<contassign loc="d,53,13,53,14" dtype_id="2">
<varref loc="d,53,15,53,16" name="t.between" dtype_id="2"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="2"/>
</contassign>
</scope>
</topscope>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d48" loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype fl="d14" loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

36
test_regress/t/t_xml_flat_no_inline_mod.out
View File

@ -11,31 +11,31 @@
<file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d11" loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module fl="d11" loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope fl="d11" loc="d,11,8,11,11">
<scope fl="d11" loc="d,11,8,11,11" name="TOP">
<varscope fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<varscope fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<assignalias fl="d11" loc="d,11,24,11,29" dtype_id="1">
<varref fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<module loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope loc="d,11,8,11,11">
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<assignalias loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
</assignalias>
<assignalias fl="d7" loc="d,7,24,7,29" dtype_id="1">
<varref fl="d7" loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
<varref fl="d7" loc="d,7,24,7,29" name="f.i_clk" dtype_id="1"/>
<assignalias loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="f.i_clk" dtype_id="1"/>
</assignalias>
</scope>
</topscope>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d11" loc="d,11,18,11,23" id="1" name="logic"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,11,18,11,23" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

36
test_regress/t/t_xml_flat_pub_mod.out
View File

@ -11,31 +11,31 @@
<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d11" loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module fl="d11" loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope fl="d11" loc="d,11,8,11,11">
<scope fl="d11" loc="d,11,8,11,11" name="TOP">
<varscope fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<varscope fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<assignalias fl="d11" loc="d,11,24,11,29" dtype_id="1">
<varref fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<module loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope loc="d,11,8,11,11">
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<assignalias loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
</assignalias>
<assignalias fl="d7" loc="d,7,24,7,29" dtype_id="1">
<varref fl="d7" loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
<varref fl="d7" loc="d,7,24,7,29" name="f.i_clk" dtype_id="1"/>
<assignalias loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="f.i_clk" dtype_id="1"/>
</assignalias>
</scope>
</topscope>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d11" loc="d,11,18,11,23" id="1" name="logic"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,11,18,11,23" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

284
test_regress/t/t_xml_flat_vlvbound.out
View File

@ -11,205 +11,205 @@
<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d7" loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/>
<cell loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,21" name="$root" origName="$root" topModule="1" public="true">
<var fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_a" public="true"/>
<var fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="i_b" public="true"/>
<var fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="o_a" public="true"/>
<var fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" pinIndex="4" vartype="logic" origName="o_b" public="true"/>
<var fl="d9" loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1" vartype="logic" origName="i_a"/>
<var fl="d10" loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1" vartype="logic" origName="i_b"/>
<var fl="d11" loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2" vartype="logic" origName="o_a"/>
<var fl="d12" loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2" vartype="logic" origName="o_b"/>
<topscope fl="d7" loc="d,7,8,7,21">
<scope fl="d7" loc="d,7,8,7,21" name="TOP">
<varscope fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varscope fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varscope fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varscope fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varscope fl="d9" loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
<varscope fl="d10" loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
<varscope fl="d11" loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
<varscope fl="d12" loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
<varscope fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varscope fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<varscope fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varscope fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<varscope fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varscope fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<varscope fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varscope fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<assignalias fl="d9" loc="d,9,25,9,28" dtype_id="1">
<varref fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varref fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<module loc="d,7,8,7,21" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_a" public="true"/>
<var loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="i_b" public="true"/>
<var loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="o_a" public="true"/>
<var loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" pinIndex="4" vartype="logic" origName="o_b" public="true"/>
<var loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1" vartype="logic" origName="i_a"/>
<var loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1" vartype="logic" origName="i_b"/>
<var loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2" vartype="logic" origName="o_a"/>
<var loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2" vartype="logic" origName="o_b"/>
<topscope loc="d,7,8,7,21">
<scope loc="d,7,8,7,21" name="TOP">
<varscope loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varscope loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varscope loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varscope loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varscope loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
<varscope loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
<varscope loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
<varscope loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varscope loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varscope loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<assignalias loc="d,9,25,9,28" dtype_id="1">
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
</assignalias>
<assignalias fl="d10" loc="d,10,25,10,28" dtype_id="1">
<varref fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varref fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<assignalias loc="d,10,25,10,28" dtype_id="1">
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
</assignalias>
<assignalias fl="d11" loc="d,11,25,11,28" dtype_id="2">
<varref fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varref fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<assignalias loc="d,11,25,11,28" dtype_id="2">
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
</assignalias>
<assignalias fl="d12" loc="d,12,25,12,28" dtype_id="2">
<varref fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varref fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<assignalias loc="d,12,25,12,28" dtype_id="2">
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
</assignalias>
<always fl="d24" loc="d,24,14,24,15">
<comment fl="d24" loc="d,24,16,24,19" name="Function: foo"/>
<assign fl="d24" loc="d,24,20,24,23" dtype_id="1">
<varref fl="d24" loc="d,24,20,24,23" name="i_a" dtype_id="1"/>
<varref fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<always loc="d,24,14,24,15">
<comment loc="d,24,16,24,19" name="Function: foo"/>
<assign loc="d,24,20,24,23" dtype_id="1">
<varref loc="d,24,20,24,23" name="i_a" dtype_id="1"/>
<varref loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
</assign>
<assign fl="d18" loc="d,18,11,18,12" dtype_id="3">
<const fl="d18" loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<assign loc="d,18,11,18,12" dtype_id="3">
<const loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
<while fl="d18" loc="d,18,5,18,8">
<while loc="d,18,5,18,8">
<begin>
</begin>
<begin>
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<gts loc="d,18,18,18,19" dtype_id="5">
<const loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</gts>
</begin>
<begin>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="5">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="5">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="6">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="7">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<assign loc="d,19,14,19,15" dtype_id="5">
<eq loc="d,19,31,19,33" dtype_id="5">
<const loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel loc="d,19,20,19,21" dtype_id="6">
<varref loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<sel loc="d,19,22,19,23" dtype_id="7">
<muls loc="d,19,22,19,23" dtype_id="4">
<const loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="8"/>
<const loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
<const loc="d,19,22,19,23" name="32&apos;h4" dtype_id="8"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
<const loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</sel>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="5">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="9">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="8"/>
<sel loc="d,19,10,19,11" dtype_id="5">
<varref loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<sel loc="d,19,11,19,12" dtype_id="9">
<varref loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<const loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
<const loc="d,19,11,19,12" name="32&apos;h3" dtype_id="8"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="8"/>
<const loc="d,19,10,19,11" name="32&apos;h1" dtype_id="8"/>
</sel>
</assign>
</begin>
<begin>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="8">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<assign loc="d,18,24,18,26" dtype_id="3">
<add loc="d,18,24,18,26" dtype_id="8">
<const loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
</begin>
</while>
<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varref fl="d21" loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<assign loc="d,21,5,21,11" dtype_id="2">
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
</assign>
<assign fl="d24" loc="d,24,14,24,15" dtype_id="2">
<varref fl="d24" loc="d,24,16,24,19" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varref fl="d24" loc="d,24,10,24,13" name="o_a" dtype_id="2"/>
<assign loc="d,24,14,24,15" dtype_id="2">
<varref loc="d,24,16,24,19" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varref loc="d,24,10,24,13" name="o_a" dtype_id="2"/>
</assign>
</always>
<always fl="d25" loc="d,25,14,25,15">
<comment fl="d25" loc="d,25,16,25,19" name="Function: foo"/>
<assign fl="d25" loc="d,25,20,25,23" dtype_id="1">
<varref fl="d25" loc="d,25,20,25,23" name="i_b" dtype_id="1"/>
<varref fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<always loc="d,25,14,25,15">
<comment loc="d,25,16,25,19" name="Function: foo"/>
<assign loc="d,25,20,25,23" dtype_id="1">
<varref loc="d,25,20,25,23" name="i_b" dtype_id="1"/>
<varref loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
</assign>
<assign fl="d18" loc="d,18,11,18,12" dtype_id="3">
<const fl="d18" loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<assign loc="d,18,11,18,12" dtype_id="3">
<const loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
<while fl="d18" loc="d,18,5,18,8">
<while loc="d,18,5,18,8">
<begin>
</begin>
<begin>
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<gts loc="d,18,18,18,19" dtype_id="5">
<const loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</gts>
</begin>
<begin>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="5">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="5">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="6">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="7">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<assign loc="d,19,14,19,15" dtype_id="5">
<eq loc="d,19,31,19,33" dtype_id="5">
<const loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel loc="d,19,20,19,21" dtype_id="6">
<varref loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<sel loc="d,19,22,19,23" dtype_id="7">
<muls loc="d,19,22,19,23" dtype_id="4">
<const loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="8"/>
<const loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
<const loc="d,19,22,19,23" name="32&apos;h4" dtype_id="8"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
<const loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</sel>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="5">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="9">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="8"/>
<sel loc="d,19,10,19,11" dtype_id="5">
<varref loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<sel loc="d,19,11,19,12" dtype_id="9">
<varref loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<const loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
<const loc="d,19,11,19,12" name="32&apos;h3" dtype_id="8"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="8"/>
<const loc="d,19,10,19,11" name="32&apos;h1" dtype_id="8"/>
</sel>
</assign>
</begin>
<begin>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="8">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<assign loc="d,18,24,18,26" dtype_id="3">
<add loc="d,18,24,18,26" dtype_id="8">
<const loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
</begin>
</while>
<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varref fl="d21" loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<assign loc="d,21,5,21,11" dtype_id="2">
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
</assign>
<assign fl="d25" loc="d,25,14,25,15" dtype_id="2">
<varref fl="d25" loc="d,25,16,25,19" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varref fl="d25" loc="d,25,10,25,13" name="o_b" dtype_id="2"/>
<assign loc="d,25,14,25,15" dtype_id="2">
<varref loc="d,25,16,25,19" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varref loc="d,25,10,25,13" name="o_b" dtype_id="2"/>
</assign>
</always>
</scope>
</topscope>
<var fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout"/>
<var fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__val"/>
<var fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__ret"/>
<var fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__0__i"/>
<var fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout"/>
<var fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__val"/>
<var fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__ret"/>
<var fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__1__i"/>
<var loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout"/>
<var loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__val"/>
<var loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__ret"/>
<var loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__0__i"/>
<var loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout"/>
<var loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__val"/>
<var loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__ret"/>
<var loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__1__i"/>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d18" loc="d,18,18,18,19" id="5" name="logic"/>
<basicdtype fl="d19" loc="d,19,34,19,39" id="6" name="logic" left="1" right="0"/>
<basicdtype fl="d9" loc="d,9,11,9,16" id="1" name="logic" left="15" right="0"/>
<basicdtype fl="d11" loc="d,11,12,11,17" id="2" name="logic" left="6" right="0"/>
<basicdtype fl="d17" loc="d,17,5,17,12" id="3" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d19" loc="d,19,10,19,11" id="9" name="logic" left="2" right="0" signed="true"/>
<basicdtype fl="d19" loc="d,19,11,19,12" id="8" name="logic" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,20,19,21" id="7" name="logic" left="3" right="0" signed="true"/>
<basicdtype fl="d18" loc="d,18,12,18,13" id="4" name="logic" left="31" right="0" signed="true"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,18,18,18,19" id="5" name="logic"/>
<basicdtype loc="d,19,34,19,39" id="6" name="logic" left="1" right="0"/>
<basicdtype loc="d,9,11,9,16" id="1" name="logic" left="15" right="0"/>
<basicdtype loc="d,11,12,11,17" id="2" name="logic" left="6" right="0"/>
<basicdtype loc="d,17,5,17,12" id="3" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,19,10,19,11" id="9" name="logic" left="2" right="0" signed="true"/>
<basicdtype loc="d,19,11,19,12" id="8" name="logic" left="31" right="0"/>
<basicdtype loc="d,19,20,19,21" id="7" name="logic" left="3" right="0" signed="true"/>
<basicdtype loc="d,18,12,18,13" id="4" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

10
test_regress/t/t_xml_output.out
View File

@ -11,14 +11,14 @@
<file id="d" filename="t/t_xml_output.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d7" loc="d,7,8,7,9" name="m" submodname="m" hier="m"/>
<cell loc="d,7,8,7,9" name="m" submodname="m" hier="m"/>
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="m" origName="m">
<var fl="d8" loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<module loc="d,7,8,7,9" name="m" origName="m">
<var loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d8" loc="d,8,10,8,13" id="1" name="logic"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,8,10,8,13" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

98
test_regress/t/t_xml_tag.out
View File

@ -11,72 +11,72 @@
<file id="d" filename="t/t_xml_tag.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d12" loc="d,12,8,12,9" name="m" submodname="m" hier="m">
<cell fl="d29" loc="d,29,8,29,12" name="itop" submodname="ifc" hier="m.itop"/>
<cell loc="d,12,8,12,9" name="m" submodname="m" hier="m">
<cell loc="d,29,8,29,12" name="itop" submodname="ifc" hier="m.itop"/>
</cell>
</cells>
<netlist>
<module fl="d12" loc="d,12,8,12,9" name="m" origName="m" topModule="1">
<var fl="d14" loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip"/>
<var fl="d15" loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip"/>
<var fl="d16" loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op"/>
<typedef fl="d25" loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/>
<instance fl="d29" loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/>
<var fl="d29" loc="d,29,8,29,12" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
<var fl="d31" loc="d,31,14,31,25" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
<var fl="d33" loc="d,33,16,33,22" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
<contassign fl="d33" loc="d,33,23,33,24" dtype_id="5">
<varxref fl="d33" loc="d,33,30,33,35" name="value" dtype_id="6" dotted="itop"/>
<varref fl="d33" loc="d,33,16,33,22" name="dotted" dtype_id="5"/>
<module loc="d,12,8,12,9" name="m" origName="m" topModule="1">
<var loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip"/>
<var loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip"/>
<var loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op"/>
<typedef loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/>
<instance loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/>
<var loc="d,29,8,29,12" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
<var loc="d,31,14,31,25" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
<var loc="d,33,16,33,22" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
<contassign loc="d,33,23,33,24" dtype_id="5">
<varxref loc="d,33,30,33,35" name="value" dtype_id="6" dotted="itop"/>
<varref loc="d,33,16,33,22" name="dotted" dtype_id="5"/>
</contassign>
<func fl="d35" loc="d,35,13,35,14" name="f" dtype_id="1">
<var fl="d35" loc="d,35,13,35,14" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
<var fl="d35" loc="d,35,28,35,29" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
<display fl="d36" loc="d,36,7,36,15" displaytype="$display">
<sformatf fl="d36" loc="d,36,7,36,15" name="%@" dtype_id="7">
<varref fl="d36" loc="d,36,22,36,23" name="m" dtype_id="7"/>
<func loc="d,35,13,35,14" name="f" dtype_id="1">
<var loc="d,35,13,35,14" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
<var loc="d,35,28,35,29" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
<display loc="d,36,7,36,15" displaytype="$display">
<sformatf loc="d,36,7,36,15" name="%@" dtype_id="7">
<varref loc="d,36,22,36,23" name="m" dtype_id="7"/>
</sformatf>
</display>
</func>
<initial fl="d39" loc="d,39,4,39,11">
<begin fl="d39" loc="d,39,12,39,17">
<taskref fl="d41" loc="d,41,7,41,8" name="f">
<arg fl="d41" loc="d,41,9,41,736">
<const fl="d41" loc="d,41,9,41,736" name="&quot;&#1;&#2;&#3;&#4;&#5;&#6;&#7;&#8;&#9;&#10;&#11;&#12;&#13;&#14;&#15;&#16;&#17;&#18;&#19;&#20;&#21;&#22;&#23;&#24;&#25;&#26;&#27;&#28;&#29;&#30;&#31; !&quot;#$%&amp;&apos;()*+,-./0123456789:;&lt;=&gt;?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~&#127;&#128;&#129;&#130;&#131;&#132;&#133;&#134;&#135;&#136;&#137;&#138;&#139;&#140;&#141;&#142;&#143;&#144;&#145;&#146;&#147;&#148;&#149;&#150;&#151;&#152;&#153;&#154;&#155;&#156;&#157;&#158;&#159;&#160;&#161;&#162;&#163;&#164;&#165;&#166;&#167;&#168;&#169;&#170;&#171;&#172;&#173;&#174;&#175;&#176;&#177;&#178;&#179;&#180;&#181;&#182;&#183;&#184;&#185;&#186;&#187;&#188;&#189;&#190;&#191;&#192;&#193;&#194;&#195;&#196;&#197;&#198;&#199;&#200;&#201;&#202;&#203;&#204;&#205;&#206;&#207;&#208;&#209;&#210;&#211;&#212;&#213;&#214;&#215;&#216;&#217;&#218;&#219;&#220;&#221;&#222;&#223;&#224;&#225;&#226;&#227;&#228;&#229;&#230;&#231;&#232;&#233;&#234;&#235;&#236;&#237;&#238;&#239;&#240;&#241;&#242;&#243;&#244;&#245;&#246;&#247;&#248;&#249;&#250;&#251;&#252;&#253;&#254;&#255;&quot;" dtype_id="7"/>
<initial loc="d,39,4,39,11">
<begin loc="d,39,12,39,17">
<taskref loc="d,41,7,41,8" name="f">
<arg loc="d,41,9,41,736">
<const loc="d,41,9,41,736" name="&quot;&#1;&#2;&#3;&#4;&#5;&#6;&#7;&#8;&#9;&#10;&#11;&#12;&#13;&#14;&#15;&#16;&#17;&#18;&#19;&#20;&#21;&#22;&#23;&#24;&#25;&#26;&#27;&#28;&#29;&#30;&#31; !&quot;#$%&amp;&apos;()*+,-./0123456789:;&lt;=&gt;?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~&#127;&#128;&#129;&#130;&#131;&#132;&#133;&#134;&#135;&#136;&#137;&#138;&#139;&#140;&#141;&#142;&#143;&#144;&#145;&#146;&#147;&#148;&#149;&#150;&#151;&#152;&#153;&#154;&#155;&#156;&#157;&#158;&#159;&#160;&#161;&#162;&#163;&#164;&#165;&#166;&#167;&#168;&#169;&#170;&#171;&#172;&#173;&#174;&#175;&#176;&#177;&#178;&#179;&#180;&#181;&#182;&#183;&#184;&#185;&#186;&#187;&#188;&#189;&#190;&#191;&#192;&#193;&#194;&#195;&#196;&#197;&#198;&#199;&#200;&#201;&#202;&#203;&#204;&#205;&#206;&#207;&#208;&#209;&#210;&#211;&#212;&#213;&#214;&#215;&#216;&#217;&#218;&#219;&#220;&#221;&#222;&#223;&#224;&#225;&#226;&#227;&#228;&#229;&#230;&#231;&#232;&#233;&#234;&#235;&#236;&#237;&#238;&#239;&#240;&#241;&#242;&#243;&#244;&#245;&#246;&#247;&#248;&#249;&#250;&#251;&#252;&#253;&#254;&#255;&quot;" dtype_id="7"/>
</arg>
</taskref>
</begin>
</initial>
</module>
<iface fl="d7" loc="d,7,11,7,14" name="ifc" origName="ifc">
<var fl="d8" loc="d,8,12,8,17" name="value" dtype_id="6" vartype="integer" origName="value"/>
<modport fl="d9" loc="d,9,12,9,23" name="out_modport">
<modportvarref fl="d9" loc="d,9,32,9,37" name="value" direction="out"/>
<iface loc="d,7,11,7,14" name="ifc" origName="ifc">
<var loc="d,8,12,8,17" name="value" dtype_id="6" vartype="integer" origName="value"/>
<modport loc="d,9,12,9,23" name="out_modport">
<modportvarref loc="d,9,32,9,37" name="value" direction="out"/>
</modport>
</iface>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d8" loc="d,8,4,8,11" id="6" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d14" loc="d,14,11,14,17" id="1" name="logic"/>
<basicdtype fl="d21" loc="d,21,7,21,12" id="8" name="logic"/>
<basicdtype fl="d22" loc="d,22,7,22,12" id="9" name="logic"/>
<basicdtype fl="d23" loc="d,23,7,23,12" id="10" name="logic"/>
<basicdtype fl="d24" loc="d,24,7,24,12" id="11" name="logic"/>
<structdtype fl="d20" loc="d,20,12,20,18" id="2" name="m.my_struct">
<memberdtype fl="d21" loc="d,21,16,21,19" id="12" name="clk" tag="this is clk" sub_dtype_id="8"/>
<memberdtype fl="d22" loc="d,22,16,22,17" id="13" name="k" sub_dtype_id="9"/>
<memberdtype fl="d23" loc="d,23,16,23,22" id="14" name="enable" tag="enable" sub_dtype_id="10"/>
<memberdtype fl="d24" loc="d,24,16,24,20" id="15" name="data" tag="data" sub_dtype_id="11"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,8,4,8,11" id="6" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,14,11,14,17" id="1" name="logic"/>
<basicdtype loc="d,21,7,21,12" id="8" name="logic"/>
<basicdtype loc="d,22,7,22,12" id="9" name="logic"/>
<basicdtype loc="d,23,7,23,12" id="10" name="logic"/>
<basicdtype loc="d,24,7,24,12" id="11" name="logic"/>
<structdtype loc="d,20,12,20,18" id="2" name="m.my_struct">
<memberdtype loc="d,21,16,21,19" id="12" name="clk" tag="this is clk" sub_dtype_id="8"/>
<memberdtype loc="d,22,16,22,17" id="13" name="k" sub_dtype_id="9"/>
<memberdtype loc="d,23,16,23,22" id="14" name="enable" tag="enable" sub_dtype_id="10"/>
<memberdtype loc="d,24,16,24,20" id="15" name="data" tag="data" sub_dtype_id="11"/>
</structdtype>
<ifacerefdtype fl="d29" loc="d,29,8,29,12" id="3" modportname=""/>
<basicdtype fl="d31" loc="d,31,27,31,28" id="5" name="logic" left="31" right="0"/>
<refdtype fl="d31" loc="d,31,4,31,13" id="16" name="my_struct" sub_dtype_id="2"/>
<unpackarraydtype fl="d31" loc="d,31,26,31,27" id="4" sub_dtype_id="2">
<range fl="d31" loc="d,31,26,31,27">
<const fl="d31" loc="d,31,27,31,28" name="32&apos;h0" dtype_id="5"/>
<const fl="d31" loc="d,31,27,31,28" name="32&apos;h1" dtype_id="5"/>
<ifacerefdtype loc="d,29,8,29,12" id="3" modportname=""/>
<basicdtype loc="d,31,27,31,28" id="5" name="logic" left="31" right="0"/>
<refdtype loc="d,31,4,31,13" id="16" name="my_struct" sub_dtype_id="2"/>
<unpackarraydtype loc="d,31,26,31,27" id="4" sub_dtype_id="2">
<range loc="d,31,26,31,27">
<const loc="d,31,27,31,28" name="32&apos;h0" dtype_id="5"/>
<const loc="d,31,27,31,28" name="32&apos;h1" dtype_id="5"/>
</range>
</unpackarraydtype>
<basicdtype fl="d35" loc="d,35,21,35,27" id="7" name="string"/>
<basicdtype loc="d,35,21,35,27" id="7" name="string"/>
</typetable>
</netlist>
</verilator_xml>