Tests: Add t_var_notfound_bad

This commit is contained in:
Wilson Snyder 2012-07-22 09:09:53 -04:00
parent 0f583f4b33
commit 3e03fef3e3
2 changed files with 49 additions and 0 deletions

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#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
fails=>1,
expect=>
'%Error: t/t_var_notfound_bad.v:\d+: Can\'t find definition of signal: nf
%Error: t/t_var_notfound_bad.v:\d+: Can\'t find definition of \'subsubz\' in dotted signal: sub.subsubz.inss
%Error: Known scopes under \'inss\': subsub
%Error: t/t_var_notfound_bad.v:\d+: Can\'t find definition of task/function: nofunc
%Error: t/t_var_notfound_bad.v:\d+: Can\'t find definition of task/function: notask
%Error: Exiting due to.*',
);
ok(1);
1;

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/);
integer i;
sub sub ();
initial begin
nf = 0; // z not found
sub.subsubz.inss = 0; // subsub not found
i = nofunc(); // nofunc not found
notask(); // notask not found
$finish;
end
endmodule
module sub;
subsub subsub ();
endmodule
module subsub;
integer inss;
endmodule