Fix packed array non-zero right index select crash, bug642.

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix module resolution with __, bug631. [Jason McMullan]
 
+**** Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski]
+
 
 * Verilator 3.846 2013-03-09
 

src/V3WidthSel.cpp

@@ -217,7 +217,7 @@ private:
 				       fromp,
 				       new AstMul(nodep->fileline(),
 						  new AstConst(nodep->fileline(),AstConst::Unsized32(),elwidth),
-						  newSubLsbOf(rhsp, fromRange)),
+						  subp),
 				       new AstConst (nodep->fileline(),AstConst::Unsized32(),elwidth));
 	    newp->declRange(fromRange);
 	    newp->declElWidth(elwidth);

test_regress/t/t_gen_lsb.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_gen_lsb.v

@@ -0,0 +1,91 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [3:0]   datai = crc[3:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   logic [3:0]		datao;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .datao			(datao[3:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .datai			(datai[3:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {60'h0, datao};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h3db7bc8bfe61f983
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test
+  (
+   input logic 	      clk,
+   input logic [3:0]  datai,
+   output logic [3:0] datao
+);
+   genvar 	      i;
+
+   parameter SIZE = 4;
+
+   logic [SIZE:1][3:0] 	delay;
+
+   always_ff @(posedge clk) begin
+      delay[1][3:0] <= datai;
+   end
+
+   generate
+      for (i = 2; i < (SIZE+1); i++) begin
+         always_ff @(posedge clk) begin
+            delay[i][3:0] <= delay[i-1][3:0];
+         end
+      end
+   endgenerate
+
+   always_comb datao = delay[SIZE][3:0];
+
+endmodule