Fix arrayed instances connecting to slices, #2263.

Changes

@@ -24,11 +24,11 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated.
 
-****  Greatly improve FST dump performance, #2244, #2250, #2257. [Geza Lore]
+****  Greatly improve FST/VCD dump performance, #2244, #2246, #2250, #2257. [Geza Lore]
 
 ****  Fix build of fast path tracing code to use OPT_FAST, #2245. [Geza Lore]
 
-****  Improve VCD dump performance, #2246, #2250, #2257. [Geza Lore]
+****  Fix arrayed instances connecting to slices, #2263. [Don/engr248]
 
 
 * Verilator 4.032 2020-04-04

src/V3Inst.cpp

@@ -371,10 +371,11 @@ private:
             } else {
                 nodep->v3fatalSrc("Width mismatch; V3Width should have errored out.");
             }
-        } else if (AstArraySel* arrselp = VN_CAST(nodep->exprp(), ArraySel)) {
+        }  // end expanding ranged cell
+        else if (AstArraySel* arrselp = VN_CAST(nodep->exprp(), ArraySel)) {
             if (AstUnpackArrayDType* arrp = VN_CAST(arrselp->lhsp()->dtypep(), UnpackArrayDType)) {
                 if (!VN_IS(arrp->subDTypep(), IfaceRefDType)) return;
-
+                // Interface pin attaches to one element of arrayed interface
                 V3Const::constifyParamsEdit(arrselp->rhsp());
                 const AstConst* constp = VN_CAST(arrselp->rhsp(), Const);
                 if (!constp) {
@@ -395,6 +396,7 @@ private:
             AstVar* pinVarp = nodep->modVarp();
             AstUnpackArrayDType* pinArrp = VN_CAST(pinVarp->dtypep(), UnpackArrayDType);
             if (!pinArrp || !VN_IS(pinArrp->subDTypep(), IfaceRefDType)) return;
+            // Arrayed pin/var attaches to arrayed submodule lower port/var, expand it
             AstNode* prevp = NULL;
             AstNode* prevPinp = NULL;
             // Clone the var referenced by the pin, and clone each var referenced by the varref
@@ -432,8 +434,16 @@ private:
                 newp->modVarp(varNewp);
                 newp->name(newp->name() + "__BRA__" + cvtToStr(i) + "__KET__");
                 // And replace exprp with a new varxref
+                int offset = 0;
                 const AstVarRef* varrefp = VN_CAST(newp->exprp(), VarRef);
-                string newname = varrefp->name() + "__BRA__" + cvtToStr(i) + "__KET__";
+                if (varrefp) {
+                } else if (AstSliceSel* slicep = VN_CAST(newp->exprp(), SliceSel)) {
+                    varrefp = VN_CAST(slicep->fromp(), VarRef);
+                    UASSERT(VN_IS(slicep->rhsp(), Const), "Slices should be constant");
+                    offset = VN_CAST(slicep->rhsp(), Const)->toSInt();
+                }
+                if (!varrefp) { newp->exprp()->v3error("Unexpected connection to arrayed port"); }
+                string newname = varrefp->name() + "__BRA__" + cvtToStr(i + offset) + "__KET__";
                 AstVarXRef* newVarXRefp = new AstVarXRef(nodep->fileline(), newname, "", true);
                 newVarXRefp->varp(newp->modVarp());
                 newVarXRefp->dtypep(newp->modVarp()->dtypep());

test_regress/t/t_inst_dearray_slice.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dearray_slice.v

@@ -0,0 +1,90 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by engr248.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   wire [31:0] in = 0;
+   wire [31:0] out;
+
+   Test test(
+             .out(out[31:0]),
+             .clk(clk),
+             .in (in[31:0])
+             );
+
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+interface Intf ();
+endinterface
+
+module Select
+  #(
+    parameter int NUM_MASTER = 1
+    )
+   (
+    Intf Upstream,
+    Intf Downstream[NUM_MASTER]
+    );
+endmodule
+
+module Crossbar
+ #(
+   parameter int NUM_MASTER = 1,
+   parameter int NUM_SLAVE = 1
+   )
+ (
+  Intf Masters[NUM_MASTER]
+  );
+
+   Intf selectOut[(NUM_MASTER * (NUM_SLAVE+1))-1 : 0]();
+
+
+   genvar i;
+
+   for (i = 0; i < NUM_MASTER; i = i + 1) begin
+      Select #(
+               .NUM_MASTER(NUM_SLAVE+1)
+               )
+      select_inst (
+                   .Upstream(Masters[i]),
+                   // Following line triggered the dearrayAll segfault
+                   .Downstream(selectOut[(i+1)*(NUM_SLAVE+1) - 1 : i*(NUM_SLAVE+1)])
+                   );
+   end
+
+endmodule
+
+module Test
+  (
+   input             clk,
+   input [31:0]      in,
+   output reg [31:0] out
+   );
+
+   always @(posedge clk) begin
+      out <= in;
+   end
+
+   Intf MST[2](); //MST must have >1 array size to trigger dearrayAll segfault
+
+   Crossbar #(
+              .NUM_MASTER(2),
+              .NUM_SLAVE(1)
+              )
+   xbar_inst (
+              .Masters(MST)
+              );
+
+endmodule