forked from github/verilator
Check c style array
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@ -26,6 +26,7 @@ module t (/*AUTOARG*/
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integer i0,i1,i2;
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integer i0,i1,i2;
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integer imem[2:0][1:3];
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integer imem[2:0][1:3];
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reg [2:0] cstyle[2];
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initial begin
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initial begin
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for (i0=0; i0<3; i0=i0+1) begin
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for (i0=0; i0<3; i0=i0+1) begin
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@ -75,6 +76,8 @@ module t (/*AUTOARG*/
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memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
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memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
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memw[index0][index1][index2] <= {~crc[7:0],crc};
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memw[index0][index1][index2] <= {~crc[7:0],crc};
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//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
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//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
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cstyle[cyc[0]] <= cyc[2:0];
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if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop;
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end
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end
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else if (cyc==90) begin
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else if (cyc==90) begin
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memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
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memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
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