Fix cell assigning integer array parameters (#3299).

Changes

@@ -38,6 +38,7 @@ Verilator 5.001 devel
 * Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang]
 * Add --get-supported to determine what features are in Verilator.
 * Add error on real edge event control.
+* Fix cell assigning integer array parameters (#3299). [Michael Platzer]
 * Fix LSB error on --hierarchical submodules (#3539). [danbone]
 * Fix $display of fixed-width numbers (#3565). [Iztok Jeras]
 * Fix foreach and pre/post increment in functions (#3613). [Nandu Raj]

src/V3Width.cpp

@@ -4740,12 +4740,19 @@ private:
         // TOP LEVEL NODE
         if (nodep->modVarp() && nodep->modVarp()->isGParam()) {
             // Widthing handled as special init() case
+            bool didWidth = false;
             if (auto* const patternp = VN_CAST(nodep->exprp(), Pattern)) {
-                if (const auto* modVarp = nodep->modVarp()) {
+                if (const AstVar* const modVarp = nodep->modVarp()) {
-                    patternp->childDTypep(modVarp->childDTypep()->cloneTree(false));
+                    // Convert BracketArrayDType
+                    userIterate(modVarp->childDTypep(),
+                                WidthVP{SELF, BOTH}.p());  // May relink pointed to node
+                    AstNodeDType* const setDtp = modVarp->childDTypep()->cloneTree(false);
+                    patternp->childDTypep(setDtp);
+                    userIterateChildren(nodep, WidthVP{setDtp, BOTH}.p());
+                    didWidth = true;
                 }
             }
-            userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+            if (!didWidth) userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
         } else if (!m_paramsOnly) {
             if (!nodep->modVarp()->didWidth()) {
                 // Var hasn't been widthed, so make it so.

test_regress/t/t_param_array8.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_array8.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub
+    #(
+        parameter int unsigned VAL[2] = '{1, 2}
+    )
+    ();
+endmodule
+
+module t;
+   sub sub12 ();
+   sub #(.VAL ( '{3, 4} )) sub34 ();
+
+   initial begin
+      if (sub12.VAL[0] != 1) $stop;
+      if (sub12.VAL[1] != 2) $stop;
+      if (sub34.VAL[0] != 3) $stop;
+      if (sub34.VAL[1] != 4) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule