forked from github/verilator
Fix trace overflow on huge arrays, bug834.
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@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix not tracing modules following primitives, bug837. [Jie Xu]
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**** Fix trace overflow on huge arrays, bug834. [Geoff Barrett]
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* Verilator 3.864 2014-09-21
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@ -261,6 +261,20 @@ void VerilatedVcd::printTime (vluint64_t timeui) {
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printQuad(timeui);
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}
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void VerilatedVcd::bufferResize(vluint64_t minsize) {
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// minsize is size of largest write. We buffer at least 8 times as much data,
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// writing when we are 3/4 full (with thus 2*minsize remaining free)
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if (VL_UNLIKELY(minsize > m_wrChunkSize)) {
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char* oldbufp = m_wrBufp;
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m_wrChunkSize = minsize*2;
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m_wrBufp = new char [m_wrChunkSize * 8];
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memcpy(m_wrBufp, oldbufp, m_writep - oldbufp);
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m_writep = m_wrBufp + (m_writep - oldbufp);
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m_wrFlushp = m_wrBufp + m_wrChunkSize * 6;
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delete oldbufp; oldbufp=NULL;
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}
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}
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void VerilatedVcd::bufferFlush () {
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// We add output data to m_writep.
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// When it gets nearly full we dump it using this routine which calls write()
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@ -444,6 +458,9 @@ void VerilatedVcd::declare (vluint32_t code, const char* name, const char* wirep
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m_sigs.reserve(m_nextCode*2); // Power-of-2 allocation speeds things up
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}
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// Make sure write buffer is large enough (one character per bit), plus header
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bufferResize(bits+1024);
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// Save declaration info
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VerilatedVcdSig sig = VerilatedVcdSig(code, bits);
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m_sigs.push_back(sig);
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@ -522,7 +539,7 @@ void VerilatedVcd::declDouble (vluint32_t code, const char* name, int arraynum
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void VerilatedVcd::fullDouble (vluint32_t code, const double newval) {
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(*((double*)&m_sigs_oldvalp[code])) = newval;
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// Buffer can't overflow; we have at least bufferInsertSize() bytes (>>>16 bytes)
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// Buffer can't overflow before sprintf; we sized during declaration
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sprintf(m_writep, "r%.16g", newval);
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m_writep += strlen(m_writep);
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*m_writep++=' '; printCode(code); *m_writep++='\n';
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@ -530,7 +547,7 @@ void VerilatedVcd::fullDouble (vluint32_t code, const double newval) {
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}
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void VerilatedVcd::fullFloat (vluint32_t code, const float newval) {
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(*((float*)&m_sigs_oldvalp[code])) = newval;
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// Buffer can't overflow; we have at least bufferInsertSize() bytes (>>>16 bytes)
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// Buffer can't overflow before sprintf; we sized during declaration
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sprintf(m_writep, "r%.16g", (double)newval);
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m_writep += strlen(m_writep);
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*m_writep++=' '; printCode(code); *m_writep++='\n';
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@ -77,7 +77,9 @@ private:
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vluint64_t m_timeLastDump; ///< Last time we did a dump
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char* m_wrBufp; ///< Output buffer
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char* m_wrFlushp; ///< Output buffer flush trigger location
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char* m_writep; ///< Write pointer into output buffer
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vluint64_t m_wrChunkSize; ///< Output buffer size
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vluint64_t m_wroteBytes; ///< Number of bytes written to this file
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vluint32_t* m_sigs_oldvalp; ///< Pointer to old signal values
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@ -87,13 +89,12 @@ private:
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NameMap* m_namemapp; ///< List of names for the header
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static vector<VerilatedVcd*> s_vcdVecp; ///< List of all created traces
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inline static size_t bufferSize() { return 256*1024; } // See below for slack calculation
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inline static size_t bufferInsertSize() { return 16*1024; }
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void bufferResize(vluint64_t minsize);
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void bufferFlush();
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void bufferCheck() {
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inline void bufferCheck() {
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// Flush the write buffer if there's not enough space left for new information
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// We only call this once per vector, so we need enough slop for a very wide "b###" line
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if (VL_UNLIKELY(m_writep > (m_wrBufp+(bufferSize()-bufferInsertSize())))) {
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if (VL_UNLIKELY(m_writep > m_wrFlushp)) {
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bufferFlush();
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}
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}
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@ -135,17 +136,19 @@ protected:
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public:
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// CREATORS
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VerilatedVcd () : m_isOpen(false), m_rolloverMB(0), m_modDepth(0), m_nextCode(1) {
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m_wrBufp = new char [bufferSize()];
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m_writep = m_wrBufp;
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m_namemapp = NULL;
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m_timeRes = m_timeUnit = 1e-9;
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m_timeLastDump = 0;
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m_sigs_oldvalp = NULL;
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m_evcd = false;
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m_scopeEscape = '.'; // Backward compatibility
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m_wroteBytes = 0;
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m_fd = 0;
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m_fullDump = true;
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m_wrChunkSize = 8*1024;
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m_wrBufp = new char [m_wrChunkSize*8];
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m_wrFlushp = m_wrBufp + m_wrChunkSize * 6;
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m_writep = m_wrBufp;
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m_wroteBytes = 0;
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}
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~VerilatedVcd();
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21
test_regress/t/t_trace_array.pl
Executable file
21
test_regress/t/t_trace_array.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ['--cc --trace --trace-structs'],
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);
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execute (
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check_finished=>1,
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);
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
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ok(1);
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1;
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26
test_regress/t/t_trace_array.v
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26
test_regress/t/t_trace_array.v
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@ -0,0 +1,26 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (clk);
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input clk;
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integer cyc=0;
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// Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk
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typedef struct packed {
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logic [1024*1024:0] d;
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} s1_t; // 128 b
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s1_t biggie;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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biggie [ cyc +: 32 ] <= 32'hfeedface;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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