forked from github/verilator
Show IEEE reference in array port message, plus internal cleanups.
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@ -532,7 +532,7 @@ private:
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}
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return newmodp;
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}
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void visitCell(AstCell* nodep, const string& hierName);
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void visitCellDeparam(AstCell* nodep, const string& hierName);
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void visitModules() {
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// Loop on all modules left to process
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// Hitting a cell adds to the appropriate level of this level-sorted list,
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@ -558,7 +558,7 @@ private:
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if (string* genHierNamep = (string*)cellp->user5p()) {
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fullName += *genHierNamep;
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}
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visitCell(cellp, fullName);
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visitCellDeparam(cellp, fullName);
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}
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}
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}
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@ -887,7 +887,7 @@ public:
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//----------------------------------------------------------------------
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// VISITs
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void ParamVisitor::visitCell(AstCell* nodep, const string& hierName) {
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void ParamVisitor::visitCellDeparam(AstCell* nodep, const string& hierName) {
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// Cell: Check for parameters in the instantiation.
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iterateChildren(nodep);
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UASSERT_OBJ(nodep->modp(), nodep, "Not linked?");
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@ -198,8 +198,7 @@ private:
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// STATE
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WidthVP* m_vup = nullptr; // Current node state
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bool m_paramsOnly; // Computing parameter value; limit operation
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AstRange* m_cellRangep
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= nullptr; // Range for arrayed instantiations, nullptr for normal instantiations
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AstCell* m_cellp = nullptr; // Current cell for arrayed instantiations
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AstNodeFTask* m_ftaskp = nullptr; // Current function/task
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AstNodeProcedure* m_procedurep = nullptr; // Current final/always
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AstLambdaArgRef* m_lambdaArgRefp = nullptr; // Argument to above lambda
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@ -4052,8 +4051,8 @@ private:
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if (conDTypep == pinDTypep // If match, we're golden
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|| similarDTypeRecurse(conDTypep, pinDTypep)) {
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userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p());
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} else if (m_cellRangep) {
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int numInsts = m_cellRangep->elementsConst();
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} else if (m_cellp->rangep()) {
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int numInsts = m_cellp->rangep()->elementsConst();
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if (conwidth == pinwidth) {
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// Arrayed instants: widths match so connect to each instance
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subDTypep = conDTypep; // = same expr dtype
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@ -4069,7 +4068,7 @@ private:
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<< " requires " << pinwidth << " or " << pinwidth * numInsts
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<< " bits, but connection's "
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<< nodep->exprp()->prettyTypeName() << " generates " << conwidth
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<< " bits.");
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<< " bits. (IEEE 1800-2017 23.3.3)");
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subDTypep = conDTypep; // = same expr dtype
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}
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userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p());
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@ -4138,6 +4137,8 @@ private:
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// if (debug()) nodep->dumpTree(cout, "- PinOut: ");
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}
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virtual void visit(AstCell* nodep) override {
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VL_RESTORER(m_cellp);
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m_cellp = nodep;
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if (!m_paramsOnly) {
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if (VN_IS(nodep->modp(), NotFoundModule)) {
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// We've resolved parameters and hit a module that we couldn't resolve. It's
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@ -4147,14 +4148,10 @@ private:
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<< nodep->modName() << "'");
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v3Global.opt.filePathLookedMsg(nodep->modNameFileline(), nodep->modName());
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}
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if (nodep->rangep()) {
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m_cellRangep = nodep->rangep();
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userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
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}
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if (nodep->rangep()) userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
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userIterateAndNext(nodep->pinsp(), nullptr);
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}
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userIterateAndNext(nodep->paramsp(), nullptr);
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m_cellRangep = nullptr;
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}
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virtual void visit(AstGatePin* nodep) override {
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if (m_vup->prelim()) {
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@ -1,4 +1,4 @@
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%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
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%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2017 23.3.3)
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: ... In instance t
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19 | sub sub [7:0] (allbits, onebitbad, bitout);
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| ^~~~~~~~~
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