forked from github/verilator
Fix tracing of packed arrays without --trace-structs, bug742.
This commit is contained in:
Wilson Snyder
parent
6b2ee0fcf3
commit
2e10555f03
2
Changes
2
Changes
@ -23,6 +23,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix tracing of package variables and real arrays.
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**** Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu]
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**** Fix missing coverage line on else-if, bug727. [Sharad Bagri]
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**** Fix modport function import not-found error.
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@ -615,7 +615,9 @@ struct VNumRange {
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int hiMaxSelect() const { return (lo()<0 ? hi()-lo() : hi()); } // Maximum value a [] select may index
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bool representableByWidth() const // Could be represented by just width=1, or [width-1:0]
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{ return (!m_ranged || (m_lo==0 && m_hi>=1 && !m_littleEndian)); }
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void dump(ostream& str) const { if (ranged()) str<<"["<<left()<<":"<<right()<<"]"; else str<<"[norg]"; }
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};
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inline ostream& operator<<(ostream& os, VNumRange rhs) { rhs.dump(os); return os; }
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//######################################################################
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@ -835,11 +835,11 @@ void AstNodeDType::dumpSmall(ostream& str) {
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void AstNodeArrayDType::dumpSmall(ostream& str) {
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this->AstNodeDType::dumpSmall(str);
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if (castPackArrayDType()) str<<"p"; else str<<"u";
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str<<"["<<declRange().left()<<":"<<declRange().right()<<"]";
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str<<" "<<declRange();
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}
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void AstNodeArrayDType::dump(ostream& str) {
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this->AstNodeDType::dump(str);
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str<<" ["<<declRange().left()<<":"<<declRange().right()<<"]";
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str<<" "<<declRange();
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}
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void AstNodeModule::dump(ostream& str) {
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this->AstNode::dump(str);
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@ -855,7 +855,7 @@ void AstPackageImport::dump(ostream& str) {
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void AstSel::dump(ostream& str) {
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this->AstNode::dump(str);
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if (declRange().ranged()) {
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str<<" decl["<<declRange().left()<<":"<<declRange().right()<<"]";
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str<<" decl"<<declRange()<<"]";
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if (declElWidth()!=1) str<<"/"<<declElWidth();
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}
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}
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@ -108,12 +108,15 @@ private:
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void addCFuncStmt(AstCFunc* basep, AstNode* nodep, VNumRange arrayRange) {
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basep->addStmtsp(nodep);
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}
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void addTraceDecl(const VNumRange& arrayRange) {
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void addTraceDecl(const VNumRange& arrayRange,
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int widthOverride) { // If !=0, is packed struct/array where basicp size misreflects one element
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VNumRange bitRange;
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AstBasicDType* bdtypep = m_traValuep->dtypep()->basicp();
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if (bdtypep) bitRange = bdtypep->nrange();
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if (widthOverride) bitRange = VNumRange(widthOverride-1,0,false);
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else if (bdtypep) bitRange = bdtypep->nrange();
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AstTraceDecl* declp = new AstTraceDecl(m_traVscp->fileline(), m_traShowname, m_traValuep,
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bitRange, arrayRange);
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UINFO(9,"Decl "<<declp<<endl);
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if (m_initSubStmts && v3Global.opt.outputSplitCTrace()
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&& m_initSubStmts > v3Global.opt.outputSplitCTrace()) {
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@ -199,7 +202,7 @@ private:
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&& m_traVscp->dtypep()->skipRefp() == nodep) { // Nothing above this array
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// Simple 1-D array, use exising V3EmitC runtime loop rather than unrolling
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// This will put "(index)" at end of signal name for us
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addTraceDecl(nodep->declRange());
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addTraceDecl(nodep->declRange(), 0);
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} else {
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// Unroll now, as have no other method to get right signal names
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AstNodeDType* subtypep = nodep->subDTypep()->skipRefp();
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@ -225,7 +228,7 @@ private:
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if (!v3Global.opt.traceStructs()) {
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// Everything downstream is packed, so deal with as one trace unit
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// This may not be the nicest for user presentation, but is a much faster way to trace
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addTraceDecl(VNumRange());
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addTraceDecl(VNumRange(), nodep->width());
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} else {
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AstNodeDType* subtypep = nodep->subDTypep()->skipRefp();
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for (int i=nodep->lsb(); i<=nodep->msb(); ++i) {
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@ -250,7 +253,7 @@ private:
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if (nodep->packed() && !v3Global.opt.traceStructs()) {
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// Everything downstream is packed, so deal with as one trace unit
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// This may not be the nicest for user presentation, but is a much faster way to trace
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addTraceDecl(VNumRange());
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addTraceDecl(VNumRange(), nodep->width());
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} else {
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if (!nodep->packed()) {
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addIgnore("Unsupported: Unpacked struct/union");
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@ -282,7 +285,7 @@ private:
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if (nodep->keyword()==AstBasicDTypeKwd::STRING) {
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addIgnore("Unsupported: strings");
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} else {
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addTraceDecl(VNumRange());
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addTraceDecl(VNumRange(), 0);
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}
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}
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}
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@ -1,45 +1,46 @@
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$version Generated by VerilatedVcd $end
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$date Fri Mar 14 20:31:17 2014
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$date Tue Apr 15 19:42:28 2014
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 7 clk $end
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$var wire 1 9 clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module v $end
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$var wire 1 7 clk $end
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$var wire 1 9 clk $end
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$var wire 32 $ cyc [31:0] $end
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$var real 64 1 v_arr_real(0) $end
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$var real 64 3 v_arr_real(1) $end
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$var wire 2 ( v_arrp [2:1] $end
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$var wire 2 ) v_arrp_arrp [2:1] $end
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$var wire 2 * v_arrp_strp [1:0] $end
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$var wire 1 8 v_arru(1) $end
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$var wire 1 9 v_arru(2) $end
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$var wire 2 + v_arru_arrp(3) [2:1] $end
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$var wire 2 , v_arru_arrp(4) [2:1] $end
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$var wire 1 : v_arru_arru(3)(1) $end
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$var wire 1 ; v_arru_arru(3)(2) $end
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$var wire 1 < v_arru_arru(4)(1) $end
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$var wire 1 = v_arru_arru(4)(2) $end
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$var wire 2 - v_arru_strp(3) [1:0] $end
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$var wire 2 . v_arru_strp(4) [1:0] $end
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$var real 64 / v_real $end
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$var wire 2 % v_strp [1:0] $end
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$var wire 4 & v_strp_strp [3:0] $end
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$var wire 2 ' v_unip_strp [1:0] $end
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$var real 64 3 v_arr_real(0) $end
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$var real 64 5 v_arr_real(1) $end
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$var wire 2 * v_arrp [2:1] $end
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$var wire 4 + v_arrp_arrp [3:0] $end
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$var wire 4 , v_arrp_strp [3:0] $end
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$var wire 1 : v_arru(1) $end
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$var wire 1 ; v_arru(2) $end
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$var wire 2 - v_arru_arrp(3) [2:1] $end
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$var wire 2 . v_arru_arrp(4) [2:1] $end
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$var wire 1 < v_arru_arru(3)(1) $end
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$var wire 1 = v_arru_arru(3)(2) $end
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$var wire 1 > v_arru_arru(4)(1) $end
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$var wire 1 ? v_arru_arru(4)(2) $end
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$var wire 2 / v_arru_strp(3) [1:0] $end
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$var wire 2 0 v_arru_strp(4) [1:0] $end
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$var real 64 1 v_real $end
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$var wire 64 % v_str32x2 [63:0] $end
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$var wire 2 ' v_strp [1:0] $end
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$var wire 4 ( v_strp_strp [3:0] $end
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$var wire 2 ) v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 > PARAM [31:0] $end
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$var wire 32 @ PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 ? PARAM [31:0] $end
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$var wire 32 A PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 5 b [31:0] $end
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$var wire 32 7 b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 6 a [31:0] $end
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$var wire 32 8 a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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@ -50,135 +51,142 @@ $enddefinitions $end
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#0
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1#
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b00000000000000000000000000000000 $
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b00 %
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b0000 &
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b0000000000000000000000000000000000000000000000000000000011111111 %
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b00 (
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b0000 )
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b0000 *
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b00 ,
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b0000 (
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b00 )
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b00 *
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b0000 +
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b0000 ,
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b00 -
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b00 .
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r0 /
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b00 /
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b00 0
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r0 1
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r0 3
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b00000000000000000000000000000000 5
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b00000000000000000000000000000000 6
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07
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08
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r0 5
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b00000000000000000000000000000000 7
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b00000000000000000000000000000000 8
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09
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0:
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0;
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0<
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0=
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b00000000000000000000000000000010 >
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b00000000000000000000000000000011 ?
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0>
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0?
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b00000000000000000000000000000010 @
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b00000000000000000000000000000011 A
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#10
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b00000000000000000000000000000001 $
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b11 %
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b1111 &
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b0000000000000000000000000000000100000000000000000000000011111110 %
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b11 '
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b11 (
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b1111 )
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b1111 *
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b11 +
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b11 ,
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b1111 (
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b11 )
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b11 *
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b1111 +
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b1111 ,
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b11 -
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b11 .
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r0.1 /
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r0.2 1
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r0.3 3
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b00000000000000000000000000000101 5
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b00000000000000000000000000000101 6
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17
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b11 /
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b11 0
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r0.1 1
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r0.2 3
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r0.3 5
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b00000000000000000000000000000101 7
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b00000000000000000000000000000101 8
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19
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#15
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07
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09
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#20
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b00000000000000000000000000000010 $
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b00 %
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b0000 &
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b0000000000000000000000000000001000000000000000000000000011111101 %
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b00 '
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b00 (
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b0000 )
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b0000 *
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b00 +
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b00 ,
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b0000 (
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b00 )
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b00 *
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b0000 +
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b0000 ,
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b00 -
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b00 .
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r0.2 /
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r0.4 1
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r0.6 3
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17
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b00 /
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b00 0
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r0.2 1
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r0.4 3
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r0.6 5
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19
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#25
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07
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09
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#30
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b00000000000000000000000000000011 $
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b11 %
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b1111 &
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b0000000000000000000000000000001100000000000000000000000011111100 %
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b11 '
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b11 (
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b1111 )
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b1111 *
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b11 +
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b11 ,
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b1111 (
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b11 )
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b11 *
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b1111 +
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b1111 ,
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b11 -
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b11 .
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r0.3 /
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r0.6000000000000001 1
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r0.8999999999999999 3
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17
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b11 /
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b11 0
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r0.3 1
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r0.6000000000000001 3
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r0.8999999999999999 5
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19
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#35
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07
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09
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#40
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b00000000000000000000000000000100 $
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b00 %
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b0000 &
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b0000000000000000000000000000010000000000000000000000000011111011 %
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b00 '
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b00 (
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b0000 )
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b0000 *
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b00 +
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b00 ,
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b0000 (
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b00 )
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b00 *
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b0000 +
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b0000 ,
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b00 -
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b00 .
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r0.4 /
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r0.8 1
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r1.2 3
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17
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b00 /
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b00 0
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r0.4 1
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r0.8 3
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r1.2 5
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19
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#45
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07
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09
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#50
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b00000000000000000000000000000101 $
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b11 %
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b1111 &
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b0000000000000000000000000000010100000000000000000000000011111010 %
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b11 '
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b11 (
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b1111 )
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b1111 *
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b11 +
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b11 ,
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b1111 (
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b11 )
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b11 *
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b1111 +
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b1111 ,
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b11 -
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b11 .
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r0.5 /
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r1 1
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r1.5 3
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17
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b11 /
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b11 0
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r0.5 1
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r1 3
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r1.5 5
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19
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#55
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07
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09
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#60
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b00000000000000000000000000000110 $
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b00 %
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b0000 &
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b0000000000000000000000000000011000000000000000000000000011111001 %
|
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b00 '
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b00 (
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b0000 )
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b0000 *
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b00 +
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b00 ,
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b0000 (
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b00 )
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b00 *
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b0000 +
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b0000 ,
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b00 -
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b00 .
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r0.6 /
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r1.2 1
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r1.8 3
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17
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b00 /
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b00 0
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r0.6 1
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r1.2 3
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r1.8 5
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19
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@ -49,6 +49,13 @@ module t (clk);
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real v_arr_real [2];
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string v_string;
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typedef struct packed {
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logic [31:0] data;
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} str32_t;
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str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
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initial v_str32x2[0] = 32'hff;
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initial v_str32x2[1] = 0;
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p #(.PARAM(2)) p2 ();
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p #(.PARAM(3)) p3 ();
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@ -72,6 +79,8 @@ module t (clk);
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v_arru_arru[a][b] = ~v_arru_arru[a][b];
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end
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end
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v_str32x2[0] <= v_str32x2[0] - 1;
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v_str32x2[1] <= v_str32x2[1] + 1;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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@ -1,45 +1,46 @@
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$version Generated by VerilatedVcd $end
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$date Fri Mar 14 20:32:05 2014
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$date Tue Apr 15 19:42:37 2014
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$end
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$timescale 1ns $end
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|
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$scope module top $end
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$var wire 1 7 clk $end
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$var wire 1 9 clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module v $end
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$var wire 1 7 clk $end
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$var wire 1 9 clk $end
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$var wire 32 $ cyc [31:0] $end
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$var real 64 1 v_arr_real(0) $end
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$var real 64 3 v_arr_real(1) $end
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$var wire 2 ( v_arrp [2:1] $end
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$var wire 2 ) v_arrp_arrp [2:1] $end
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$var wire 2 * v_arrp_strp [1:0] $end
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$var wire 1 8 v_arru(1) $end
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$var wire 1 9 v_arru(2) $end
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$var wire 2 + v_arru_arrp(3) [2:1] $end
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$var wire 2 , v_arru_arrp(4) [2:1] $end
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$var wire 1 : v_arru_arru(3)(1) $end
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$var wire 1 ; v_arru_arru(3)(2) $end
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$var wire 1 < v_arru_arru(4)(1) $end
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$var wire 1 = v_arru_arru(4)(2) $end
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$var wire 2 - v_arru_strp(3) [1:0] $end
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$var wire 2 . v_arru_strp(4) [1:0] $end
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$var real 64 / v_real $end
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$var wire 2 % v_strp [1:0] $end
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$var wire 4 & v_strp_strp [3:0] $end
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$var wire 2 ' v_unip_strp [1:0] $end
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$var real 64 3 v_arr_real(0) $end
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$var real 64 5 v_arr_real(1) $end
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$var wire 2 * v_arrp [2:1] $end
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$var wire 4 + v_arrp_arrp [3:0] $end
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$var wire 4 , v_arrp_strp [3:0] $end
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$var wire 1 : v_arru(1) $end
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$var wire 1 ; v_arru(2) $end
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$var wire 2 - v_arru_arrp(3) [2:1] $end
|
||||
$var wire 2 . v_arru_arrp(4) [2:1] $end
|
||||
$var wire 1 < v_arru_arru(3)(1) $end
|
||||
$var wire 1 = v_arru_arru(3)(2) $end
|
||||
$var wire 1 > v_arru_arru(4)(1) $end
|
||||
$var wire 1 ? v_arru_arru(4)(2) $end
|
||||
$var wire 2 / v_arru_strp(3) [1:0] $end
|
||||
$var wire 2 0 v_arru_strp(4) [1:0] $end
|
||||
$var real 64 1 v_real $end
|
||||
$var wire 64 % v_str32x2 [63:0] $end
|
||||
$var wire 2 ' v_strp [1:0] $end
|
||||
$var wire 4 ( v_strp_strp [3:0] $end
|
||||
$var wire 2 ) v_unip_strp [1:0] $end
|
||||
$scope module p2 $end
|
||||
$var wire 32 > PARAM [31:0] $end
|
||||
$var wire 32 @ PARAM [31:0] $end
|
||||
$upscope $end
|
||||
$scope module p3 $end
|
||||
$var wire 32 ? PARAM [31:0] $end
|
||||
$var wire 32 A PARAM [31:0] $end
|
||||
$upscope $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var wire 32 5 b [31:0] $end
|
||||
$var wire 32 7 b [31:0] $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var wire 32 6 a [31:0] $end
|
||||
$var wire 32 8 a [31:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
@ -50,135 +51,142 @@ $enddefinitions $end
|
||||
#0
|
||||
1#
|
||||
b00000000000000000000000000000000 $
|
||||
b00 %
|
||||
b0000 &
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
07
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
#10
|
||||
b00000000000000000000000000000001 $
|
||||
b11 %
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
17
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
r0.3 5
|
||||
b00000000000000000000000000000101 7
|
||||
b00000000000000000000000000000101 8
|
||||
19
|
||||
#15
|
||||
07
|
||||
09
|
||||
#20
|
||||
b00000000000000000000000000000010 $
|
||||
b00 %
|
||||
b0000 &
|
||||
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|
||||
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|
||||
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|
||||
b0000 )
|
||||
b0000 *
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
17
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
19
|
||||
#25
|
||||
07
|
||||
09
|
||||
#30
|
||||
b00000000000000000000000000000011 $
|
||||
b11 %
|
||||
b1111 &
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b11 *
|
||||
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|
||||
b1111 ,
|
||||
b11 -
|
||||
b11 .
|
||||
r0.3 /
|
||||
r0.6000000000000001 1
|
||||
r0.8999999999999999 3
|
||||
17
|
||||
b11 /
|
||||
b11 0
|
||||
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|
||||
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|
||||
r0.8999999999999999 5
|
||||
19
|
||||
#35
|
||||
07
|
||||
09
|
||||
#40
|
||||
b00000000000000000000000000000100 $
|
||||
b00 %
|
||||
b0000 &
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b0000 *
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b0000 ,
|
||||
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|
||||
b00 .
|
||||
r0.4 /
|
||||
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|
||||
r1.2 3
|
||||
17
|
||||
b00 /
|
||||
b00 0
|
||||
r0.4 1
|
||||
r0.8 3
|
||||
r1.2 5
|
||||
19
|
||||
#45
|
||||
07
|
||||
09
|
||||
#50
|
||||
b00000000000000000000000000000101 $
|
||||
b11 %
|
||||
b1111 &
|
||||
b0000000000000000000000000000010100000000000000000000000011111010 %
|
||||
b11 '
|
||||
b11 (
|
||||
b1111 )
|
||||
b1111 *
|
||||
b11 +
|
||||
b11 ,
|
||||
b1111 (
|
||||
b11 )
|
||||
b11 *
|
||||
b1111 +
|
||||
b1111 ,
|
||||
b11 -
|
||||
b11 .
|
||||
r0.5 /
|
||||
r1 1
|
||||
r1.5 3
|
||||
17
|
||||
b11 /
|
||||
b11 0
|
||||
r0.5 1
|
||||
r1 3
|
||||
r1.5 5
|
||||
19
|
||||
#55
|
||||
07
|
||||
09
|
||||
#60
|
||||
b00000000000000000000000000000110 $
|
||||
b00 %
|
||||
b0000 &
|
||||
b0000000000000000000000000000011000000000000000000000000011111001 %
|
||||
b00 '
|
||||
b00 (
|
||||
b0000 )
|
||||
b0000 *
|
||||
b00 +
|
||||
b00 ,
|
||||
b0000 (
|
||||
b00 )
|
||||
b00 *
|
||||
b0000 +
|
||||
b0000 ,
|
||||
b00 -
|
||||
b00 .
|
||||
r0.6 /
|
||||
r1.2 1
|
||||
r1.8 3
|
||||
17
|
||||
b00 /
|
||||
b00 0
|
||||
r0.6 1
|
||||
r1.2 3
|
||||
r1.8 5
|
||||
19
|
||||
|
||||
@ -1,74 +1,80 @@
|
||||
$version Generated by VerilatedVcd $end
|
||||
$date Fri Mar 14 20:32:11 2014
|
||||
$date Tue Apr 15 12:58:17 2014
|
||||
$end
|
||||
$timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 B clk $end
|
||||
$var wire 1 D clk $end
|
||||
$scope module $unit $end
|
||||
$var wire 1 # global_bit $end
|
||||
$upscope $end
|
||||
$scope module v $end
|
||||
$var wire 1 B clk $end
|
||||
$var wire 1 D clk $end
|
||||
$var wire 32 $ cyc [31:0] $end
|
||||
$var real 64 < v_arr_real(0) $end
|
||||
$var real 64 > v_arr_real(1) $end
|
||||
$var wire 2 - v_arrp [2:1] $end
|
||||
$var wire 2 . v_arrp_arrp(3) [1:0] $end
|
||||
$var wire 2 / v_arrp_arrp(4) [1:0] $end
|
||||
$var wire 1 C v_arru(1) $end
|
||||
$var wire 1 D v_arru(2) $end
|
||||
$var wire 2 4 v_arru_arrp(3) [2:1] $end
|
||||
$var wire 2 5 v_arru_arrp(4) [2:1] $end
|
||||
$var wire 1 E v_arru_arru(3)(1) $end
|
||||
$var wire 1 F v_arru_arru(3)(2) $end
|
||||
$var wire 1 G v_arru_arru(4)(1) $end
|
||||
$var wire 1 H v_arru_arru(4)(2) $end
|
||||
$var real 64 : v_real $end
|
||||
$var real 64 > v_arr_real(0) $end
|
||||
$var real 64 @ v_arr_real(1) $end
|
||||
$var wire 2 / v_arrp [2:1] $end
|
||||
$var wire 2 0 v_arrp_arrp(3) [1:0] $end
|
||||
$var wire 2 1 v_arrp_arrp(4) [1:0] $end
|
||||
$var wire 1 E v_arru(1) $end
|
||||
$var wire 1 F v_arru(2) $end
|
||||
$var wire 2 6 v_arru_arrp(3) [2:1] $end
|
||||
$var wire 2 7 v_arru_arrp(4) [2:1] $end
|
||||
$var wire 1 G v_arru_arru(3)(1) $end
|
||||
$var wire 1 H v_arru_arru(3)(2) $end
|
||||
$var wire 1 I v_arru_arru(4)(1) $end
|
||||
$var wire 1 J v_arru_arru(4)(2) $end
|
||||
$var real 64 < v_real $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var wire 32 @ b [31:0] $end
|
||||
$var wire 32 B b [31:0] $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var wire 32 A a [31:0] $end
|
||||
$var wire 32 C a [31:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module v_arrp_strp(3) $end
|
||||
$var wire 1 1 b0 $end
|
||||
$var wire 1 0 b1 $end
|
||||
$upscope $end
|
||||
$scope module v_arrp_strp(4) $end
|
||||
$var wire 1 3 b0 $end
|
||||
$var wire 1 2 b1 $end
|
||||
$upscope $end
|
||||
$scope module v_arru_strp(3) $end
|
||||
$var wire 1 7 b0 $end
|
||||
$var wire 1 6 b1 $end
|
||||
$scope module v_arrp_strp(4) $end
|
||||
$var wire 1 5 b0 $end
|
||||
$var wire 1 4 b1 $end
|
||||
$upscope $end
|
||||
$scope module v_arru_strp(4) $end
|
||||
$scope module v_arru_strp(3) $end
|
||||
$var wire 1 9 b0 $end
|
||||
$var wire 1 8 b1 $end
|
||||
$upscope $end
|
||||
$scope module v_arru_strp(4) $end
|
||||
$var wire 1 ; b0 $end
|
||||
$var wire 1 : b1 $end
|
||||
$upscope $end
|
||||
$scope module v_str32x2(0) $end
|
||||
$var wire 32 % data [31:0] $end
|
||||
$upscope $end
|
||||
$scope module v_str32x2(1) $end
|
||||
$var wire 32 & data [31:0] $end
|
||||
$upscope $end
|
||||
$scope module v_strp $end
|
||||
$var wire 1 & b0 $end
|
||||
$var wire 1 % b1 $end
|
||||
$var wire 1 ( b0 $end
|
||||
$var wire 1 ' b1 $end
|
||||
$upscope $end
|
||||
$scope module v_strp_strp $end
|
||||
$scope module x0 $end
|
||||
$var wire 1 * b0 $end
|
||||
$var wire 1 ) b1 $end
|
||||
$var wire 1 , b0 $end
|
||||
$var wire 1 + b1 $end
|
||||
$upscope $end
|
||||
$scope module x1 $end
|
||||
$var wire 1 ( b0 $end
|
||||
$var wire 1 ' b1 $end
|
||||
$var wire 1 * b0 $end
|
||||
$var wire 1 ) b1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module v_unip_strp $end
|
||||
$scope module x0 $end
|
||||
$var wire 1 , b0 $end
|
||||
$var wire 1 + b1 $end
|
||||
$var wire 1 . b0 $end
|
||||
$var wire 1 - b1 $end
|
||||
$upscope $end
|
||||
$scope module x1 $end
|
||||
$var wire 1 , b0 $end
|
||||
$var wire 1 + b1 $end
|
||||
$var wire 1 . b0 $end
|
||||
$var wire 1 - b1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
@ -79,210 +85,224 @@ $enddefinitions $end
|
||||
#0
|
||||
1#
|
||||
b00000000000000000000000000000000 $
|
||||
0%
|
||||
0&
|
||||
b00000000000000000000000011111111 %
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
07
|
||||
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|
||||
05
|
||||
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|
||||
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|
||||
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|
||||
09
|
||||
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|
||||
0:
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0I
|
||||
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|
||||
#10
|
||||
b00000000000000000000000000000001 $
|
||||
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|
||||
1&
|
||||
b00000000000000000000000011111110 %
|
||||
b00000000000000000000000000000001 &
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
1.
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
14
|
||||
15
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b00000000000000000000000000000101 B
|
||||
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|
||||
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|
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|
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|
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#20
|
||||
b00000000000000000000000000000010 $
|
||||
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|
||||
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|
||||
b00000000000000000000000011111101 %
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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|
||||
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|
||||
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||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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07
|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
09
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0B
|
||||
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|
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|
||||
b00000000000000000000000000000011 $
|
||||
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|
||||
1&
|
||||
b00000000000000000000000011111100 %
|
||||
b00000000000000000000000000000011 &
|
||||
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|
||||
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|
||||
1)
|
||||
1*
|
||||
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|
||||
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|
||||
b11 -
|
||||
b11 .
|
||||
1-
|
||||
1.
|
||||
b11 /
|
||||
10
|
||||
11
|
||||
b11 0
|
||||
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|
||||
12
|
||||
13
|
||||
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|
||||
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|
||||
16
|
||||
17
|
||||
14
|
||||
15
|
||||
b11 6
|
||||
b11 7
|
||||
18
|
||||
19
|
||||
r0.3 :
|
||||
r0.6000000000000001 <
|
||||
r0.8999999999999999 >
|
||||
1B
|
||||
1:
|
||||
1;
|
||||
r0.3 <
|
||||
r0.6000000000000001 >
|
||||
r0.8999999999999999 @
|
||||
1D
|
||||
#35
|
||||
0B
|
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0D
|
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#40
|
||||
b00000000000000000000000000000100 $
|
||||
0%
|
||||
0&
|
||||
b00000000000000000000000011111011 %
|
||||
b00000000000000000000000000000100 &
|
||||
0'
|
||||
0(
|
||||
0)
|
||||
0*
|
||||
0+
|
||||
0,
|
||||
b00 -
|
||||
b00 .
|
||||
0-
|
||||
0.
|
||||
b00 /
|
||||
00
|
||||
01
|
||||
b00 0
|
||||
b00 1
|
||||
02
|
||||
03
|
||||
b00 4
|
||||
b00 5
|
||||
06
|
||||
07
|
||||
04
|
||||
05
|
||||
b00 6
|
||||
b00 7
|
||||
08
|
||||
09
|
||||
r0.4 :
|
||||
r0.8 <
|
||||
r1.2 >
|
||||
1B
|
||||
0:
|
||||
0;
|
||||
r0.4 <
|
||||
r0.8 >
|
||||
r1.2 @
|
||||
1D
|
||||
#45
|
||||
0B
|
||||
0D
|
||||
#50
|
||||
b00000000000000000000000000000101 $
|
||||
1%
|
||||
1&
|
||||
b00000000000000000000000011111010 %
|
||||
b00000000000000000000000000000101 &
|
||||
1'
|
||||
1(
|
||||
1)
|
||||
1*
|
||||
1+
|
||||
1,
|
||||
b11 -
|
||||
b11 .
|
||||
1-
|
||||
1.
|
||||
b11 /
|
||||
10
|
||||
11
|
||||
b11 0
|
||||
b11 1
|
||||
12
|
||||
13
|
||||
b11 4
|
||||
b11 5
|
||||
16
|
||||
17
|
||||
14
|
||||
15
|
||||
b11 6
|
||||
b11 7
|
||||
18
|
||||
19
|
||||
r0.5 :
|
||||
r1 <
|
||||
r1.5 >
|
||||
1B
|
||||
1:
|
||||
1;
|
||||
r0.5 <
|
||||
r1 >
|
||||
r1.5 @
|
||||
1D
|
||||
#55
|
||||
0B
|
||||
0D
|
||||
#60
|
||||
b00000000000000000000000000000110 $
|
||||
0%
|
||||
0&
|
||||
b00000000000000000000000011111001 %
|
||||
b00000000000000000000000000000110 &
|
||||
0'
|
||||
0(
|
||||
0)
|
||||
0*
|
||||
0+
|
||||
0,
|
||||
b00 -
|
||||
b00 .
|
||||
0-
|
||||
0.
|
||||
b00 /
|
||||
00
|
||||
01
|
||||
b00 0
|
||||
b00 1
|
||||
02
|
||||
03
|
||||
b00 4
|
||||
b00 5
|
||||
06
|
||||
07
|
||||
04
|
||||
05
|
||||
b00 6
|
||||
b00 7
|
||||
08
|
||||
09
|
||||
r0.6 :
|
||||
r1.2 <
|
||||
r1.8 >
|
||||
1B
|
||||
0:
|
||||
0;
|
||||
r0.6 <
|
||||
r1.2 >
|
||||
r1.8 @
|
||||
1D
|
||||
|
||||
Loading…
Reference in New Issue
Block a user