Internal coverage improvements

nodist/code_coverage.dat

@@ -56,7 +56,8 @@ exclude_line_regexp(r'\bUINFO\b')
 # Exclude for branch coverage only
 exclude_branch_regexp(r'\bdebug\(\)')
 exclude_branch_regexp(r'\bassert\(')
-exclude_branch_regexp(r'\bBROKEN_RTK\(')
+exclude_branch_regexp(r'\bBROKEN_BASE_RTN\(')
+exclude_branch_regexp(r'\bBROKEN_RTN\(')
 exclude_branch_regexp(r'\bSELF_CHECK')
 
 True

src/V3Ast.h

@@ -2450,7 +2450,6 @@ public:
     bool widthSized() const { return !m_widthMin || m_widthMin == m_width; }
     bool generic() const { return m_generic; }
     void generic(bool flag) { m_generic = flag; }
-    AstNodeDType* dtypeDimensionp(int dimension);
     std::pair<uint32_t, uint32_t> dimensions(bool includeBasic);
     uint32_t arrayUnpackedElements();  // 1, or total multiplication of all dimensions
     static int uniqueNumInc() { return ++s_uniqueNum; }

src/V3AstNodes.cpp

@@ -694,47 +694,6 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const {
     return info;
 }
 
-AstNodeDType* AstNodeDType::dtypeDimensionp(int dimension) {
-    // dimension passed from AstArraySel::dimension
-    // Dimension 0 means the VAR itself, 1 is the closest SEL to the AstVar,
-    // which is the lowest in the dtype list.
-    //     ref order:   a[1][2][3][4]
-    //     Created as:  reg [4] a [1][2][3];
-    //        *or*      reg a [1][2][3][4];
-    //                  // The bit select is optional; used only if "leftover" []'s
-    //     SEL:         SEL4(SEL3(SEL2(SEL1(VARREF0 a))))
-    //     DECL:        VAR a (ARRAYSEL0 (ARRAYSEL1 (ARRAYSEL2 (DT RANGE3))))
-    //        *or*      VAR a (ARRAYSEL0 (ARRAYSEL1 (ARRAYSEL2 (ARRAYSEL3 (DT))))
-    //     SEL1 needs to select from entire variable which is a pointer to ARRAYSEL0
-    // TODO this function should be removed in favor of recursing the dtype(),
-    // as that allows for more complicated data types.
-    int dim = 0;
-    for (AstNodeDType* dtypep = this; dtypep;) {
-        dtypep = dtypep->skipRefp();  // Skip AstRefDType/AstTypedef, or return same node
-        if (AstNodeArrayDType* adtypep = VN_CAST(dtypep, NodeArrayDType)) {
-            if ((dim++) == dimension) return dtypep;
-            dtypep = adtypep->subDTypep();
-            continue;
-        } else if (AstBasicDType* adtypep = VN_CAST(dtypep, BasicDType)) {
-            // AstBasicDType - nothing below, return null
-            if (adtypep->isRanged()) {
-                // cppcheck-suppress unreadVariable  // Cppcheck bug - thinks dim isn't used
-                if ((dim++) == dimension) return adtypep;
-            }
-            return nullptr;
-        } else if (AstNodeUOrStructDType* adtypep = VN_CAST(dtypep, NodeUOrStructDType)) {
-            if (adtypep->packed()) {
-                // cppcheck-suppress unreadVariable  // Cppcheck bug - thinks dim isn't used
-                if ((dim++) == dimension) return adtypep;
-            }
-            return nullptr;
-        }
-        // Node no ->next in loop; use continue where necessary
-        break;
-    }
-    return nullptr;
-}
-
 uint32_t AstNodeDType::arrayUnpackedElements() {
     uint32_t entries = 1;
     for (AstNodeDType* dtypep = this; dtypep;) {

src/V3Task.cpp

@@ -66,7 +66,6 @@ public:
     AstNodeFTask* nodep() const { return m_nodep; }
     virtual string name() const override { return nodep()->name(); }
     virtual string dotColor() const override { return pure() ? "black" : "red"; }
-    virtual FileLine* fileline() const override { return nodep()->fileline(); }
     AstCFunc* cFuncp() const { return m_cFuncp; }
     void cFuncp(AstCFunc* nodep) { m_cFuncp = nodep; }
 };

src/V3Width.cpp

@@ -1091,7 +1091,7 @@ private:
                 iterateCheckSizedSelf(nodep, "Ticks", nodep->ticksp(), SELF, BOTH);
                 V3Const::constifyParamsEdit(nodep->ticksp());  // ticksp may change
                 const AstConst* constp = VN_CAST(nodep->ticksp(), Const);
-                if (!constp || constp->toSInt() < 1) {
+                if (!constp) {
                     nodep->v3error("$past tick value must be constant (IEEE 1800-2017 16.9.3)");
                     nodep->ticksp()->unlinkFrBack()->deleteTree();
                 } else if (constp->toSInt() < 1) {

test_regress/t/t_debug_emitv.out

@@ -9,6 +9,7 @@ module Vt_debug_emitv;
     signed int [31:0]  t.cyc;
     signed int [31:0]  t.fo;
     signed int [31:0]  t.sum;
+    signed real t.r;
     string t.str;
     signed int [31:0]  t._Vpast_0_0;
     signed int [31:0]  t._Vpast_1_0;
@@ -57,6 +58,7 @@ module Vt_debug_emitv;
     end
     always @(posedge clk)@(negedge clk) begin
         __Vdly__t.cyc <= (32'sh1 + t.cyc);
+        __Vdly__t.r <= (0.01 + t.r);
         t.fo = t.cyc;
         // Function: inc
         __Vtask_t.sub.inc__2__i = t.fo;
@@ -178,6 +180,24 @@ module Vt_debug_emitv;
         t.sum = 
         ???? // RAND
         32'sha;
+        $display("%g", $log10(t.r));
+        $display("%g", $ln(t.r));
+        $display("%g", $exp(t.r));
+        $display("%g", $sqrt(t.r));
+        $display("%g", $floor(t.r));
+        $display("%g", $ceil(t.r));
+        $display("%g", $sin(t.r));
+        $display("%g", $cos(t.r));
+        $display("%g", $tan(t.r));
+        $display("%g", $asin(t.r));
+        $display("%g", $acos(t.r));
+        $display("%g", $atan(t.r));
+        $display("%g", $sinh(t.r));
+        $display("%g", $cosh(t.r));
+        $display("%g", $tanh(t.r));
+        $display("%g", $asinh(t.r));
+        $display("%g", $acosh(t.r));
+        $display("%g", $atanh(t.r));
     end
     /*verilator public_flat_rw @(posedge clk)@(negedge 
                                                clk) t.pubflat*/
@@ -191,6 +211,8 @@ module Vt_debug_emitv;
     t._Vpast_1_0 = __Vdly__t._Vpast_1_0;
     __Vdly__t._Vpast_0_0 = t._Vpast_0_0;
     t._Vpast_0_0 = __Vdly__t._Vpast_0_0;
+    __Vdly__t.r = t.r;
+    t.r = __Vdly__t.r;
     __Vdly__t.cyc = t.cyc;
     t.cyc = __Vdly__t.cyc;
     __Vdly__t.pubflat_r = t.pubflat_r;
@@ -204,6 +226,7 @@ module Vt_debug_emitv;
     signed int [31:0]  __Vfunc_t.sub.f__3__v;
     logic [15:0]  __Vdly__t.pubflat_r;
     signed int [31:0]  __Vdly__t.cyc;
+    signed real __Vdly__t.r;
     signed int [31:0]  __Vdly__t._Vpast_0_0;
     signed int [31:0]  __Vdly__t._Vpast_1_0;
 endmodule

test_regress/t/t_debug_emitv.v

@@ -107,9 +107,11 @@ module t (/*AUTOARG*/
    int cyc;
    int fo;
    int sum;
+   real r;
    string str;
    always_ff @ (posedge clk) begin
       cyc <= cyc + 1;
+      r <= r + 0.01;
       fo = cyc;
       sub.inc(fo, sum);
       sum = sub.f(sum);
@@ -176,6 +178,25 @@ module t (/*AUTOARG*/
 
       if (Pkg::PKG_PARAM != 1) $stop;
       sub.r = 62.0;
+
+      $display("%g", $log10(r));
+      $display("%g", $ln(r));
+      $display("%g", $exp(r));
+      $display("%g", $sqrt(r));
+      $display("%g", $floor(r));
+      $display("%g", $ceil(r));
+      $display("%g", $sin(r));
+      $display("%g", $cos(r));
+      $display("%g", $tan(r));
+      $display("%g", $asin(r));
+      $display("%g", $acos(r));
+      $display("%g", $atan(r));
+      $display("%g", $sinh(r));
+      $display("%g", $cosh(r));
+      $display("%g", $tanh(r));
+      $display("%g", $asinh(r));
+      $display("%g", $acosh(r));
+      $display("%g", $atanh(r));
    end
 endmodule
 
@@ -188,27 +209,6 @@ module sub();
       return {31'd0, v[2]} + 32'd1;
    endfunction
    real r;
-   initial begin
-      r = 1.0;
-      r = $log10(r);
-      r = $ln(r);
-      r = $exp(r);
-      r = $sqrt(r);
-      r = $floor(r);
-      r = $ceil(r);
-      r = $sin(r);
-      r = $cos(r);
-      r = $tan(r);
-      r = $asin(r);
-      r = $acos(r);
-      r = $atan(r);
-      r = $sinh(r);
-      r = $cosh(r);
-      r = $tanh(r);
-      r = $asinh(r);
-      r = $acosh(r);
-      r = $atanh(r);
-   end
 endmodule
 
 package p;

test_regress/t/t_past_bad.out

@@ -1,10 +1,18 @@
-%Error: t/t_past_bad.v:12:11: $past tick value must be constant (IEEE 1800-2017 16.9.3)
+%Error: t/t_past_bad.v:16:20: Expecting expression to be constant, but variable isn't const: 'num'
                             : ... In instance t
-   12 |       if ($past(d, 0)) $stop;   
+   16 |       if ($past(d, num)) $stop;   
+      |                    ^~~
+%Error: t/t_past_bad.v:16:11: $past tick value must be constant (IEEE 1800-2017 16.9.3)
+                            : ... In instance t
+   16 |       if ($past(d, num)) $stop;   
       |           ^~~~~
-%Warning-TICKCOUNT: t/t_past_bad.v:13:20: $past tick value of 10000 may have a large performance cost
+%Error: t/t_past_bad.v:17:20: $past tick value must be >= 1 (IEEE 1800-2017 16.9.3)
+                            : ... In instance t
+   17 |       if ($past(d, 0)) $stop;   
+      |                    ^
+%Warning-TICKCOUNT: t/t_past_bad.v:18:20: $past tick value of 10000 may have a large performance cost
                                         : ... In instance t
-   13 |       if ($past(d, 10000)) $stop;   
+   18 |       if ($past(d, 10000)) $stop;   
       |                    ^~~~~
                     ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message.
 %Error: Exiting due to

test_regress/t/t_past_bad.v

@@ -4,12 +4,17 @@
 // any use, without warranty, 2018 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (d, clk);
+module t (/*AUTOARG*/
+   // Inputs
+   d, clk, num
+   );
    input d;
    input clk;
+   input int num;
 
    always @ (posedge clk) begin
-      if ($past(d, 0)) $stop;  // IEEE 16.9.3 must be >- 0
+      if ($past(d, num)) $stop;  // IEEE 16.9.3 must be const
+      if ($past(d, 0)) $stop;  // IEEE 16.9.3 must be >= 0
       if ($past(d, 10000)) $stop;  // TICKCOUNT
    end
 endmodule