forked from github/verilator
Internals: Common insert function in tristate. No functional change.
This commit is contained in:
Wilson Snyder
parent
33c8bf886e
commit
2c9e2b2e3c
@ -202,6 +202,174 @@ class TristateVisitor : public TristateBaseVisitor {
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nodep->v3error("Unsupported tristate construct: "<<nodep->prettyTypeName());
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}
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void insertTristates(AstNodeModule* nodep) {
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// Go through all the vars and find any that are outputs without drivers
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// or inouts without high-Z logic and put a 1'bz driver on them and add
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// them to the lhs map so they get expanded correctly.
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for (VarVec::iterator ii = m_varvec.begin(); ii != m_varvec.end(); ++ii) {
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AstVar* varp = (*ii);
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if (varp->isInout()
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//|| varp->isOutput()
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// Note unconnected output only changes behavior vs. previous versions and causes outputs
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// that don't come from anywhere to possibly create connection errors.
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// One example of problems is this: "output z; task t; z <= {something}; endtask"
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) {
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VarMap::iterator it = m_lhsmap.find(varp);
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if (it == m_lhsmap.end()) {
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UINFO(8," Adding driver to var "<<varp<<endl);
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V3Number zeros (varp->fileline(), varp->width());
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zeros.setAllBits0();
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AstConst* constp = new AstConst(varp->fileline(), zeros);
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AstVarRef* varrefp = new AstVarRef(varp->fileline(), varp, true);
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nodep->addStmtp(new AstAssignW(varp->fileline(), varrefp, constp));
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visit(varrefp, NULL);
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varrefp->user1p(new AstConst(varp->fileline(),zeros));//set output enable to always be off on this assign statement so that this var is floating
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}
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}
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}
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// Now go through the lhs driver map and generate the output
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// enable logic for any tristates.
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for (VarMap::iterator nextit, it = m_lhsmap.begin(); it != m_lhsmap.end(); it = nextit) {
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nextit = it; ++nextit;
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AstVar* invarp = (*it).first;
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RefVec* refs = (*it).second;
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// Figure out if this var needs tristate expanded.
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int needs_expanded = 0;
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// If need enable signal gets expanded
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if (invarp->user1p()) { needs_expanded++; }
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// all inouts get expanded
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if (invarp->isInout()) { needs_expanded++; }
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// loop through to find all vars that have __en logic. They get expanded.
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for (RefVec::iterator ii = refs->begin(); ii != refs->end(); ++ii) {
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AstVarRef* refp = (*ii);
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if (refp->user1p()) { needs_expanded++; }
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}
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if (needs_expanded == 0) {
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// This var has no tristate logic, so we leave it alone.
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UINFO(8, " NO TRISTATE ON:" << invarp << endl);
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m_lhsmap.erase(invarp);
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delete refs;
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continue;
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}
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m_statTriSigs++;
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UINFO(8, " TRISTATE EXPANDING("<<needs_expanded<<"):" << invarp << endl);
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// If the lhs var is a port, then we need to create ports for
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// the output (__out) and output enable (__en) signals. The
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// original port gets converted to an input. Don't tristate expand
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// if this is the top level so that we can force the final
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// tristate resolution at the top.
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AstVar* envarp = NULL;
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AstVar* outvarp = NULL;
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AstVar* lhsp = invarp;
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if (!nodep->isTop() && invarp->isIO()) {
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// This var becomes an input
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invarp->varType2In(); // convert existing port to type input
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// Create an output port (__out)
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AstVar* outvarp = getCreateOutVarp(invarp);
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outvarp->varType2Out();
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lhsp = outvarp; // Must assign to __out, not to normal input signal
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// Create an output enable port (__en)
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envarp = getCreateEnVarp(invarp); // May already be created if have foo === 1'bz somewhere
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envarp->varType2Out();
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//
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outvarp->user1p(envarp);
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outvarp->user3p(invarp->user3p());
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if (invarp->user3p()) UINFO(9, "propagate pull to "<<outvarp);
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} else if (invarp->user1p()) {
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envarp = invarp->user1p()->castNode()->castVar(); // From CASEEQ, foo === 1'bz
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}
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AstNode* orp = NULL;
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AstNode* andp = NULL;
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AstNode* enp = NULL;
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AstNode* undrivenp = NULL;
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// loop through the lhs drivers to build the driver resolution logic
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for (RefVec::iterator ii=refs->begin(); ii != refs->end(); ++ii) {
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AstVarRef* refp = (*ii);
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int w = lhsp->width();
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// create the new lhs driver for this var
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AstVar* newlhsp = new AstVar(lhsp->fileline(),
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AstVarType::MODULETEMP,
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lhsp->name()+"__out"+cvtToStr(m_unique),
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VFlagLogicPacked(), w);
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nodep->addStmtp(newlhsp);
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refp->varp(newlhsp); // assign the new var to the varref
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refp->name(newlhsp->name());
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// create a new var for this drivers enable signal
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AstVar* newenp = new AstVar(lhsp->fileline(),
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AstVarType::MODULETEMP,
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lhsp->name()+"__en"+cvtToStr(m_unique++),
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VFlagLogicPacked(), w);
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nodep->addStmtp(newenp);
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nodep->addStmtp(new AstAssignW(refp->fileline(),
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new AstVarRef(refp->fileline(), newenp, true),
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getEnp(refp)));
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// now append this driver to the driver logic.
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AstNode* ref1p = new AstVarRef(nodep->fileline(), newlhsp,false);
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AstNode* ref2p = new AstVarRef(nodep->fileline(), newenp, false);
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andp = new AstAnd(nodep->fileline(), ref1p, ref2p);
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// or this to the others
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orp = (!orp) ? andp : new AstOr(nodep->fileline(), orp, andp);
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if (envarp) {
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AstNode* ref3p = new AstVarRef(nodep->fileline(), newenp, false);
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enp = (!enp) ? ref3p : new AstOr(ref3p->fileline(), enp, ref3p);
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}
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AstNode* tmp = new AstNot(newenp->fileline(), new AstVarRef(newenp->fileline(), newenp, false));
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undrivenp = ((!undrivenp) ? tmp
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: new AstAnd(nodep->fileline(), tmp, undrivenp));
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}
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if (!undrivenp) { // No drivers on the bus
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V3Number ones(nodep->fileline(), lhsp->width()); ones.setAllBits1();
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undrivenp = new AstConst(nodep->fileline(), ones);
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}
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if (!outvarp) {
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// This is the final resolution of the tristate, so we apply
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// the pull direction to any undriven pins.
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V3Number pull(nodep->fileline(), lhsp->width());
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AstPull* pullp = (AstPull*)lhsp->user3p();
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if (pullp && pullp->direction() == 1) {
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pull.setAllBits1();
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UINFO(9,"Has pullup "<<pullp<<endl);
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} else {
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pull.setAllBits0(); // default pull direction is down.
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}
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undrivenp = new AstAnd(nodep->fileline(), undrivenp,
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new AstConst(nodep->fileline(), pull));
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orp = new AstOr(nodep->fileline(), orp, undrivenp);
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}
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if (envarp) {
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nodep->addStmtp(new AstAssignW(enp->fileline(),
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new AstVarRef(envarp->fileline(),
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envarp, true), enp));
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}
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AstNode* assp = new AstAssignW(lhsp->fileline(),
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new AstVarRef(lhsp->fileline(),
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lhsp,
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true),
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orp);
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if (debug()>=9) assp->dumpTree(cout,"-lhsp-eqn: ");
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nodep->addStmtp(assp);
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// Delete the map and vector list now that we have expanded it.
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m_lhsmap.erase(invarp);
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delete refs;
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}
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}
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// VISITORS
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virtual void visit(AstConst* nodep, AstNUser*) {
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UINFO(9,(m_alhs?"alhs":"")<<" "<<nodep<<endl);
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@ -648,172 +816,10 @@ class TristateVisitor : public TristateBaseVisitor {
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m_lhsmap.clear();
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m_varvec.clear();
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m_modp = nodep;
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// Build the LHS drivers map for this module
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nodep->iterateChildren(*this);
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// Go through all the vars and find any that are outputs without drivers
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// or inouts without high-Z logic and put a 1'bz driver on them and add
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// them to the lhs map so they get expanded correctly.
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for (VarVec::iterator ii = m_varvec.begin(); ii != m_varvec.end(); ++ii) {
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AstVar* varp = (*ii);
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if (varp->isInout()
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//|| varp->isOutput()
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// Note unconnected output only changes behavior vs. previous versions and causes outputs
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// that don't come from anywhere to possibly create connection errors.
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// One example of problems is this: "output z; task t; z <= {something}; endtask"
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) {
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VarMap::iterator it = m_lhsmap.find(varp);
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if (it == m_lhsmap.end()) {
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UINFO(8," Adding driver to var "<<varp<<endl);
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V3Number zeros (varp->fileline(), varp->width());
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zeros.setAllBits0();
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AstConst* constp = new AstConst(varp->fileline(), zeros);
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AstVarRef* varrefp = new AstVarRef(varp->fileline(), varp, true);
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nodep->addStmtp(new AstAssignW(varp->fileline(), varrefp, constp));
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visit(varrefp, NULL);
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varrefp->user1p(new AstConst(varp->fileline(),zeros));//set output enable to always be off on this assign statement so that this var is floating
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}
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}
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}
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// Now go through the lhs driver map and generate the output
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// enable logic for any tristates.
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for (VarMap::iterator nextit, it = m_lhsmap.begin(); it != m_lhsmap.end(); it = nextit) {
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nextit = it; ++nextit;
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AstVar* invarp = (*it).first;
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RefVec* refs = (*it).second;
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// Figure out if this var needs tristate expanded.
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int needs_expanded = 0;
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// If need enable signal gets expanded
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if (invarp->user1p()) { needs_expanded++; }
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// all inouts get expanded
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if (invarp->isInout()) { needs_expanded++; }
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// loop through to find all vars that have __en logic. They get expanded.
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for (RefVec::iterator ii = refs->begin(); ii != refs->end(); ++ii) {
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AstVarRef* refp = (*ii);
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if (refp->user1p()) { needs_expanded++; }
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}
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if (needs_expanded == 0) {
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// This var has no tristate logic, so we leave it alone.
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UINFO(8, " NO TRISTATE ON:" << invarp << endl);
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m_lhsmap.erase(invarp);
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delete refs;
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continue;
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}
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m_statTriSigs++;
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UINFO(8, " TRISTATE EXPANDING("<<needs_expanded<<"):" << invarp << endl);
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// If the lhs var is a port, then we need to create ports for
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// the output (__out) and output enable (__en) signals. The
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// original port gets converted to an input. Don't tristate expand
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// if this is the top level so that we can force the final
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// tristate resolution at the top.
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AstVar* envarp = NULL;
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AstVar* outvarp = NULL;
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AstVar* lhsp = invarp;
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if (!nodep->isTop() && invarp->isIO()) {
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// This var becomes an input
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invarp->varType2In(); // convert existing port to type input
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// Create an output port (__out)
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AstVar* outvarp = getCreateOutVarp(invarp);
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outvarp->varType2Out();
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lhsp = outvarp; // Must assign to __out, not to normal input signal
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// Create an output enable port (__en)
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envarp = getCreateEnVarp(invarp); // May already be created if have foo === 1'bz somewhere
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envarp->varType2Out();
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//
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outvarp->user1p(envarp);
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outvarp->user3p(invarp->user3p());
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if (invarp->user3p()) UINFO(9, "propagate pull to "<<outvarp);
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} else if (invarp->user1p()) {
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envarp = invarp->user1p()->castNode()->castVar(); // From CASEEQ, foo === 1'bz
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}
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AstNode* orp = NULL;
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AstNode* andp = NULL;
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AstNode* enp = NULL;
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AstNode* undrivenp = NULL;
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// loop through the lhs drivers to build the driver resolution logic
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for (RefVec::iterator ii=refs->begin(); ii != refs->end(); ++ii) {
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AstVarRef* refp = (*ii);
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int w = lhsp->width();
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// create the new lhs driver for this var
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AstVar* newlhsp = new AstVar(lhsp->fileline(),
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AstVarType::MODULETEMP,
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lhsp->name()+"__out"+cvtToStr(m_unique),
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VFlagLogicPacked(), w);
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nodep->addStmtp(newlhsp);
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refp->varp(newlhsp); // assign the new var to the varref
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refp->name(newlhsp->name());
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// create a new var for this drivers enable signal
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AstVar* newenp = new AstVar(lhsp->fileline(),
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AstVarType::MODULETEMP,
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lhsp->name()+"__en"+cvtToStr(m_unique++),
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VFlagLogicPacked(), w);
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nodep->addStmtp(newenp);
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nodep->addStmtp(new AstAssignW(refp->fileline(),
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new AstVarRef(refp->fileline(), newenp, true),
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getEnp(refp)));
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// now append this driver to the driver logic.
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AstNode* ref1p = new AstVarRef(nodep->fileline(), newlhsp,false);
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AstNode* ref2p = new AstVarRef(nodep->fileline(), newenp, false);
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andp = new AstAnd(nodep->fileline(), ref1p, ref2p);
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// or this to the others
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orp = (!orp) ? andp : new AstOr(nodep->fileline(), orp, andp);
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if (envarp) {
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AstNode* ref3p = new AstVarRef(nodep->fileline(), newenp, false);
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enp = (!enp) ? ref3p : new AstOr(ref3p->fileline(), enp, ref3p);
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}
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AstNode* tmp = new AstNot(newenp->fileline(), new AstVarRef(newenp->fileline(), newenp, false));
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undrivenp = ((!undrivenp) ? tmp
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: new AstAnd(nodep->fileline(), tmp, undrivenp));
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}
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if (!undrivenp) { // No drivers on the bus
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V3Number ones(nodep->fileline(), lhsp->width()); ones.setAllBits1();
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undrivenp = new AstConst(nodep->fileline(), ones);
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}
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if (!outvarp) {
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// This is the final resolution of the tristate, so we apply
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// the pull direction to any undriven pins.
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V3Number pull(nodep->fileline(), lhsp->width());
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AstPull* pullp = (AstPull*)lhsp->user3p();
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if (pullp && pullp->direction() == 1) {
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pull.setAllBits1();
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UINFO(9,"Has pullup "<<pullp<<endl);
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} else {
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pull.setAllBits0(); // default pull direction is down.
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}
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undrivenp = new AstAnd(nodep->fileline(), undrivenp,
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new AstConst(nodep->fileline(), pull));
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orp = new AstOr(nodep->fileline(), orp, undrivenp);
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}
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if (envarp) {
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nodep->addStmtp(new AstAssignW(enp->fileline(),
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new AstVarRef(envarp->fileline(),
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envarp, true), enp));
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}
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AstNode* assp = new AstAssignW(lhsp->fileline(),
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new AstVarRef(lhsp->fileline(),
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lhsp,
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true),
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orp);
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if (debug()>=9) assp->dumpTree(cout,"-lhsp-eqn: ");
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nodep->addStmtp(assp);
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// Delete the map and vector list now that we have expanded it.
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m_lhsmap.erase(invarp);
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delete refs;
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}
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// Insert new logic for all tristates
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insertTristates(nodep);
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m_modp = NULL;
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}
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