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Tests: Rename IVERILOG define for consistency. No functional change.

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This commit is contained in:
Wilson Snyder 2020-04-23 07:42:05 -04:00
parent 14643643c9
commit 2b58e834ee
10 changed files with 12 additions and 12 deletions
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2
test_regress/driver.pl
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@ -585,7 +585,7 @@ sub new {
ghdl_run_flags => [], ghdl_run_flags => [],
# IV # IV
iv => 0, iv => 0,
iv_flags => [split(/\s+/,"+define+iverilog -g2012 -o $self->{obj_dir}/simiv")], iv_flags => [split(/\s+/,"+define+IVERILOG -g2012 -o $self->{obj_dir}/simiv")],
iv_flags2 => [], # Overridden in some sim files iv_flags2 => [], # Overridden in some sim files
iv_pli => 0, # need to use pli iv_pli => 0, # need to use pli
iv_run_flags => [], iv_run_flags => [],

2
test_regress/t/t_mem_packed.v
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@ -18,7 +18,7 @@ module t (/*AUTOARG*/
//logic [3:3] [2:2] [1:1] log_p; //14 //logic [3:3] [2:2] [1:1] log_p; //14
integer cyc; initial cyc = 0; integer cyc; initial cyc = 0;
`ifdef iverilog `ifdef IVERILOG
reg [7:0] arr [3:0]; reg [7:0] arr [3:0];
wire [7:0] arr_w [3:0]; wire [7:0] arr_w [3:0];
`else `else

4
test_regress/t/t_vpi_get.v
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@ -43,7 +43,7 @@ extern "C" int mon_check();
integer status; integer status;
`ifdef iverilog `ifdef IVERILOG
// stop icarus optimizing signals away // stop icarus optimizing signals away
wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3]; wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3];
`endif `endif
@ -57,7 +57,7 @@ extern "C" int mon_check();
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif
`ifdef iverilog `ifdef IVERILOG
status = $mon_check(); status = $mon_check();
`endif `endif
`ifndef USE_VPI_NOT_DPI `ifndef USE_VPI_NOT_DPI

2
test_regress/t/t_vpi_memory.v
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@ -33,7 +33,7 @@ extern "C" int mon_check();
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif
`ifdef iverilog `ifdef IVERILOG
status = $mon_check(); status = $mon_check();
`endif `endif
`ifndef USE_VPI_NOT_DPI `ifndef USE_VPI_NOT_DPI

2
test_regress/t/t_vpi_module.v
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@ -42,7 +42,7 @@ extern "C" int mon_check();
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif
`ifdef iverilog `ifdef IVERILOG
status = $mon_check(); status = $mon_check();
`endif `endif
`ifndef USE_VPI_NOT_DPI `ifndef USE_VPI_NOT_DPI

2
test_regress/t/t_vpi_time_cb.pl
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@ -15,7 +15,7 @@ compile(
make_main => 0, make_main => 0,
make_pli => 1, make_pli => 1,
sim_time => 2100, sim_time => 2100,
iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -Diverilog"], iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"],
v_flags2 => ["+define+USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"],
verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"],
); );

2
test_regress/t/t_vpi_time_cb.v
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@ -87,7 +87,7 @@ endmodule : t
module sub; module sub;
reg subsig1 /*verilator public_flat_rd*/; reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog `ifdef IVERILOG
// stop icarus optimizing signals away // stop icarus optimizing signals away
wire redundant = subsig1 | subsig2; wire redundant = subsig1 | subsig2;
`endif `endif

4
test_regress/t/t_vpi_var.v
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@ -57,7 +57,7 @@ extern "C" int mon_check();
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif
`ifdef iverilog `ifdef IVERILOG
status = $mon_check(); status = $mon_check();
`endif `endif
`ifndef USE_VPI_NOT_DPI `ifndef USE_VPI_NOT_DPI
@ -100,7 +100,7 @@ endmodule : t
module sub; module sub;
reg subsig1 /*verilator public_flat_rd*/; reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog `ifdef IVERILOG
// stop icarus optimizing signals away // stop icarus optimizing signals away
wire redundant = subsig1 | subsig2; wire redundant = subsig1 | subsig2;
`endif `endif

2
test_regress/t/t_vpi_zero_time_cb.pl
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@ -15,7 +15,7 @@ compile(
make_main => 0, make_main => 0,
make_pli => 1, make_pli => 1,
sim_time => 2100, sim_time => 2100,
iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -Diverilog"], iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"],
v_flags2 => ["+define+USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"],
verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"],
); );

2
test_regress/t/t_vpi_zero_time_cb.v
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@ -87,7 +87,7 @@ endmodule : t
module sub; module sub;
reg subsig1 /*verilator public_flat_rd*/; reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog `ifdef IVERILOG
// stop icarus optimizing signals away // stop icarus optimizing signals away
wire redundant = subsig1 | subsig2; wire redundant = subsig1 | subsig2;
`endif `endif