From 2af53048845b1a9b66dc7670365a1d3a5145f5f2 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Fri, 26 Aug 2022 12:11:44 +0200
Subject: [PATCH] Fix tracing of slow coroutines (#3576 part) (#3579)

---
 src/V3Trace.cpp                   |  8 ++--
 test_regress/t/t_timing_trace.out | 67 +++++++++++++++++++++++++++++++
 test_regress/t/t_timing_trace.pl  | 32 +++++++++++++++
 3 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 test_regress/t/t_timing_trace.out
 create mode 100755 test_regress/t/t_timing_trace.pl

diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index b6fbb95ce..ebb1f1e7c 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -839,9 +839,11 @@ private:
         V3GraphVertex* const funcVtxp = getCFuncVertexp(nodep);
         if (!m_finding) {  // If public, we need a unique activity code to allow for sets
                            // directly in this func
-            if (nodep->funcPublic() || nodep->dpiExportImpl()
-                || nodep == v3Global.rootp()->evalp()) {
-                V3GraphVertex* const activityVtxp = getActivityVertexp(nodep, nodep->slow());
+            if (nodep->funcPublic() || nodep->dpiExportImpl() || nodep == v3Global.rootp()->evalp()
+                || nodep->isCoroutine()) {
+                // Cannot treat a coroutine as slow, it may be resumed later
+                const bool slow = nodep->slow() && !nodep->isCoroutine();
+                V3GraphVertex* const activityVtxp = getActivityVertexp(nodep, slow);
                 new V3GraphEdge(&m_graph, activityVtxp, funcVtxp, 1);
             }
         }
diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out
new file mode 100644
index 000000000..c21672923
--- /dev/null
+++ b/test_regress/t/t_timing_trace.out
@@ -0,0 +1,67 @@
+$version Generated by VerilatedVcd $end
+$date Thu Aug 25 09:56:30 2022 $end
+$timescale 1ps $end
+
+ $scope module top $end
+  $scope module t $end
+   $var wire  1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $scope module clkgen $end
+    $var wire  1 # clk $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000000 $
+#5
+1#
+b00000000000000000000000000000001 $
+#10
+0#
+#15
+1#
+b00000000000000000000000000000010 $
+#20
+0#
+#25
+1#
+b00000000000000000000000000000011 $
+#30
+0#
+#35
+1#
+b00000000000000000000000000000100 $
+#40
+0#
+#45
+1#
+b00000000000000000000000000000101 $
+#50
+0#
+#55
+1#
+b00000000000000000000000000000110 $
+#60
+0#
+#65
+1#
+b00000000000000000000000000000111 $
+#70
+0#
+#75
+1#
+b00000000000000000000000000001000 $
+#80
+0#
+#85
+1#
+b00000000000000000000000000001001 $
+#90
+0#
+#95
+1#
+b00000000000000000000000000001010 $
diff --git a/test_regress/t/t_timing_trace.pl b/test_regress/t/t_timing_trace.pl
new file mode 100755
index 000000000..5dc845188
--- /dev/null
+++ b/test_regress/t/t_timing_trace.pl
@@ -0,0 +1,32 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    top_filename("t/t_timing_clkgen1.v");
+
+    compile(
+        verilator_flags2 => ["--timing --trace -Wno-MINTYPMAXDLY"],
+        timing_loop => 1
+        );
+
+    execute(
+        check_finished => 1,
+        );
+
+    vcd_identical($Self->trace_filename, $Self->{golden_filename});
+}
+
+ok(1);
+1;