forked from github/verilator
Change range order warning from LITENDIAN to ASCRANGE (#4010)
This commit is contained in:
Iztok Jeras
GitHub
parent
9b869edd90
commit
2aa6a229ca
@ -1514,9 +1514,9 @@ Summary:
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.. option:: -Wno-lint
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Disable all lint-related warning messages, and all style warnings. This is
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equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE
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equivalent to ``-Wno-ALWCOMBORDER -Wno-ASCRANGE -Wno-BSSPACE -Wno-CASEINCOMPLETE
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-Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS
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-Wno-IMPLICIT -Wno-IMPLICITSTATIC -Wno-LITENDIAN -Wno-PINCONNECTEMPTY
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-Wno-IMPLICIT -Wno-IMPLICITSTATIC -Wno-PINCONNECTEMPTY
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-Wno-PINMISSING -Wno-STATICVAR -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED
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-Wno-UNUSEDGENVAR -Wno-UNUSEDPARAM -Wno-UNUSEDSIGNAL
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-Wno-WIDTH`` plus the list shown for Wno-style.
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@ -1554,7 +1554,7 @@ Summary:
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enabled), but do not affect style messages. This is equivalent to
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``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE
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-Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST
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-Wwarn-COLONPLUS -Wwarn-IMPLICIT -Wwarn-LITENDIAN
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-Wwarn-COLONPLUS -Wwarn-IMPLICIT -Wwarn-ASCRANGE
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-Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``.
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.. option:: -Wwarn-style
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@ -97,6 +97,24 @@ List Of Warnings
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simulate correctly.
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.. option:: ASCRANGE
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.. TODO better example
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Warns that a packed vector is declared with ascending bit range
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(i.e. [0:7]). Descending bit range is now the overwhelming standard,
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and ascending ranges are now thus often due to simple oversight
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instead of intent (a notable exception is the OpenPOWER code base).
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It also warns that an instance is declared with ascending range
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(i.e. [0:7] or [7]) and is connected to an N-wide signal.
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The bits will likely be in the reversed order from what people may expect
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(i.e., instance [0] will connect to signal bit [N-1] not bit [0]).
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Ignoring this warning will only suppress the lint check; it will
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simulate correctly.
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.. option:: ASSIGNDLY
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.. TODO better example
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@ -850,18 +868,10 @@ List Of Warnings
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.. TODO better example
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Warns that a packed vector is declared with big endian bit numbering
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(i.e. [0:7]). Little endian bit numbering is now the overwhelming
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standard, and big numbering is now thus often due to simple oversight
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instead of intent.
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It also warns that an instance is declared with big endian range
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(i.e. [0:7] or [7]) and is connected to an N-wide signal.
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The bits will likely be backward from what people may expect
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(i.e., instance [0] will connect to signal bit [N-1] not bit [0]).
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Ignoring this warning will only suppress the lint check; it will
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simulate correctly.
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The naming of this worning is in contradiction with the common
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interpretation of little endian. It was therefore renamed to
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:option:`ASCRANGE`. While :option:`LITENDIAN` remains for
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backwards compatibility, new projects should use :option:`ASCRANGE`.
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.. option:: MINTYPMAX
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@ -532,6 +532,7 @@ endcelldefine
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endfunction
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endgenerate
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endian
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endianness
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endif
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endmodule
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endprotect
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12
src/V3Ast.h
12
src/V3Ast.h
@ -1097,21 +1097,21 @@ public:
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}
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//
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VNumRange() = default;
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VNumRange(int hi, int lo, bool littleEndian) { init(hi, lo, littleEndian); }
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VNumRange(int hi, int lo, bool ascending) { init(hi, lo, ascending); }
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VNumRange(int left, int right)
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: m_left{left}
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, m_right{right}
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, m_ranged{true} {}
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~VNumRange() = default;
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// MEMBERS
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void init(int hi, int lo, bool littleEndian) {
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void init(int hi, int lo, bool ascending) {
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if (lo > hi) {
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const int t = hi;
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hi = lo;
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lo = t;
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}
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m_left = littleEndian ? lo : hi;
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m_right = littleEndian ? hi : lo;
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m_left = ascending ? lo : hi;
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m_right = ascending ? hi : lo;
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m_ranged = true;
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}
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int left() const { return m_left; }
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@ -1122,10 +1122,10 @@ public:
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int lo() const VL_MT_SAFE {
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return m_left > m_right ? m_right : m_left;
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} // How to show a declaration
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int leftToRightInc() const { return littleEndian() ? 1 : -1; }
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int leftToRightInc() const { return ascending() ? 1 : -1; }
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int elements() const VL_MT_SAFE { return hi() - lo() + 1; }
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bool ranged() const { return m_ranged; }
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bool littleEndian() const { return m_left < m_right; }
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bool ascending() const { return m_left < m_right; }
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int hiMaxSelect() const {
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return (lo() < 0 ? hi() - lo() : hi());
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} // Maximum value a [] select may index
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@ -123,8 +123,8 @@ int AstBasicDType::lo() const { return (rangep() ? rangep()->loConst() : m.m_nra
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int AstBasicDType::elements() const {
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return (rangep() ? rangep()->elementsConst() : m.m_nrange.elements());
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}
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bool AstBasicDType::littleEndian() const {
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return (rangep() ? rangep()->littleEndian() : m.m_nrange.littleEndian());
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bool AstBasicDType::ascending() const {
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return (rangep() ? rangep()->ascending() : m.m_nrange.ascending());
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}
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bool AstActive::hasClocked() const { return m_sensesp->hasClocked(); }
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@ -468,9 +468,9 @@ public:
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inline int hi() const;
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inline int lo() const;
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inline int elements() const;
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int left() const { return littleEndian() ? lo() : hi(); } // How to show a declaration
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int right() const { return littleEndian() ? hi() : lo(); }
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inline bool littleEndian() const;
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int left() const { return ascending() ? lo() : hi(); } // How to show a declaration
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int right() const { return ascending() ? hi() : lo(); }
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inline bool ascending() const;
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bool implicit() const { return keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT; }
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bool untyped() const { return keyword() == VBasicDTypeKwd::UNTYPED; }
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VNumRange declRange() const { return isRanged() ? VNumRange{left(), right()} : VNumRange{}; }
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@ -2349,7 +2349,7 @@ public:
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return l > r ? r : l;
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}
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int elementsConst() const VL_MT_STABLE { return hiConst() - loConst() + 1; }
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bool littleEndian() const { return leftConst() < rightConst(); }
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bool ascending() const { return leftConst() < rightConst(); }
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void dump(std::ostream& str) const override;
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virtual string emitC() { V3ERROR_NA_RETURN(""); }
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bool same(const AstNode* /*samep*/) const override { return true; }
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@ -1759,7 +1759,7 @@ void AstTypedef::dump(std::ostream& str) const {
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void AstNodeRange::dump(std::ostream& str) const { this->AstNode::dump(str); }
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void AstRange::dump(std::ostream& str) const {
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this->AstNodeRange::dump(str);
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if (littleEndian()) str << " [LITTLE]";
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if (ascending()) str << " [ASCENDING]";
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}
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void AstParamTypeDType::dump(std::ostream& str) const {
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this->AstNodeDType::dump(str);
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@ -70,6 +70,7 @@ public:
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EC_FIRST_WARN, // Just a code so the program knows where to start warnings
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//
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ALWCOMBORDER, // Always_comb with unordered statements
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ASCRANGE, // Ascending bit range vector
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ASSIGNDLY, // Assignment delays
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ASSIGNIN, // Assigning to input
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BADSTDPRAGMA, // Any error related to pragmas
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@ -109,7 +110,7 @@ public:
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INITIALDLY, // Initial delayed statement
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INSECURE, // Insecure options
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LATCH, // Latch detected outside of always_latch block
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LITENDIAN, // Little bit endian vector
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LITENDIAN, // Little endian, renamed to ASCRANGE
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MINTYPMAXDLY, // Unsupported: min/typ/max delay expressions
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MODDUP, // Duplicate module
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MULTIDRIVEN, // Driven from multiple blocks
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@ -183,7 +184,7 @@ public:
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"PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING",
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// Warnings
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" EC_FIRST_WARN",
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"ALWCOMBORDER", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA",
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"ALWCOMBORDER", "ASCRANGE", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA",
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"BLKANDNBLK", "BLKLOOPINIT", "BLKSEQ", "BSSPACE",
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"CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CASTCONST", "CDCRSTLOGIC", "CLKDATA",
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"CMPCONST", "COLONPLUS", "COMBDLY", "CONTASSREG",
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@ -228,12 +229,12 @@ public:
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}
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// Warnings that are lint only
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bool lintError() const VL_MT_SAFE {
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return (m_e == ALWCOMBORDER || m_e == BSSPACE || m_e == CASEINCOMPLETE
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return (m_e == ALWCOMBORDER || m_e == ASCRANGE || m_e == BSSPACE || m_e == CASEINCOMPLETE
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|| m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST
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|| m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == IMPLICITSTATIC
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|| m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT
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|| m_e == STATICVAR || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC
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|| m_e == WIDTHEXPAND || m_e == WIDTHXZEXPAND);
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|| m_e == LATCH || m_e == PINMISSING || m_e == REALCVT || m_e == STATICVAR
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|| m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC || m_e == WIDTHEXPAND
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|| m_e == WIDTHXZEXPAND);
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}
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// Warnings that are style only
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bool styleError() const VL_MT_SAFE {
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@ -251,7 +252,7 @@ public:
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V3ErrorCode renamedTo() const {
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// Return a new error this error has been renamed to
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// e.g. if (m_e == LITENDIAN) return V3ErrorCode{RANGEASC};
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if (m_e == LITENDIAN) return V3ErrorCode{ASCRANGE};
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return V3ErrorCode{EC_MIN}; // Not renamed; see isRenamed()
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}
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bool isRenamed() const { return renamedTo() != V3ErrorCode{EC_MIN}; }
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@ -252,7 +252,7 @@ private:
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// Make all of the required clones
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for (int i = 0; i < m_cellRangep->elementsConst(); i++) {
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m_instSelNum
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= m_cellRangep->littleEndian() ? (m_cellRangep->elementsConst() - 1 - i) : i;
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= m_cellRangep->ascending() ? (m_cellRangep->elementsConst() - 1 - i) : i;
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const int instNum = m_cellRangep->loConst() + i;
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AstCell* const newp = nodep->cloneTree(false);
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@ -331,7 +331,7 @@ private:
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// Connection to array, where array dimensions match the instant dimension
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const AstRange* const rangep
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= VN_AS(nodep->exprp()->dtypep(), UnpackArrayDType)->rangep();
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const int arraySelNum = rangep->littleEndian()
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const int arraySelNum = rangep->ascending()
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? (rangep->elementsConst() - 1 - m_instSelNum)
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: m_instSelNum;
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AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack();
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@ -342,11 +342,11 @@ private:
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} else if (expwidth == modwidth * m_cellRangep->elementsConst()) {
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// Arrayed instants: one bit for each of the instants (each
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// assign is 1 modwidth wide)
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if (m_cellRangep->littleEndian()) {
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nodep->exprp()->v3warn(LITENDIAN, "Big endian instance range connecting to "
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"vector: left < right of instance range: ["
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<< m_cellRangep->leftConst() << ":"
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<< m_cellRangep->rightConst() << "]");
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if (m_cellRangep->ascending()) {
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nodep->exprp()->v3warn(ASCRANGE, "Ascending instance range connecting to "
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"vector: left < right of instance range: ["
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<< m_cellRangep->leftConst() << ":"
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<< m_cellRangep->rightConst() << "]");
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}
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AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack();
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const bool inputPin = nodep->modVarp()->isNonOutput();
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@ -90,7 +90,7 @@ class SliceVisitor final : public VNVisitor {
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AstNodeExpr* newp;
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if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) {
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UINFO(9, " cloneInitArray(" << elements << "," << offset << ") " << nodep << endl);
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const int leOffset = !arrayp->rangep()->littleEndian()
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const int leOffset = !arrayp->rangep()->ascending()
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? arrayp->rangep()->elementsConst() - 1 - offset
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: offset;
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AstNodeExpr* const itemp = initp->getIndexDefaultedValuep(leOffset);
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@ -107,14 +107,14 @@ class SliceVisitor final : public VNVisitor {
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} else if (const AstSliceSel* const snodep = VN_CAST(nodep, SliceSel)) {
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UINFO(9, " cloneSliceSel(" << elements << "," << offset << ") " << nodep << endl);
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const int leOffset = (snodep->declRange().lo()
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+ (!snodep->declRange().littleEndian()
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+ (!snodep->declRange().ascending()
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? snodep->declRange().elements() - 1 - offset
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: offset));
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newp = new AstArraySel{nodep->fileline(), snodep->fromp()->cloneTree(false), leOffset};
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} else if (VN_IS(nodep, ArraySel) || VN_IS(nodep, NodeVarRef) || VN_IS(nodep, NodeSel)
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|| VN_IS(nodep, CMethodHard) || VN_IS(nodep, MemberSel)) {
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UINFO(9, " cloneSel(" << elements << "," << offset << ") " << nodep << endl);
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const int leOffset = !arrayp->rangep()->littleEndian()
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const int leOffset = !arrayp->rangep()->ascending()
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? arrayp->rangep()->elementsConst() - 1 - offset
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: offset;
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newp = new AstArraySel{nodep->fileline(), VN_AS(nodep, NodeExpr)->cloneTree(false),
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@ -139,9 +139,10 @@ class SliceVisitor final : public VNVisitor {
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if (debug() >= 9) nodep->dumpTree("- Deslice-In: ");
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AstNodeDType* const dtp = nodep->lhsp()->dtypep()->skipRefp();
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if (const AstUnpackArrayDType* const arrayp = VN_CAST(dtp, UnpackArrayDType)) {
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// Left and right could have different msb/lsbs/endianness, but #elements is common
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// and all variables are realigned to start at zero
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// Assign of a little endian'ed slice to a big endian one must reverse the elements
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// Left and right could have different ascending/descending range,
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// but #elements is common and all variables are realigned to start at zero
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// Assign of an ascending range slice to a descending range one must reverse the
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// elements
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AstNodeAssign* newlistp = nullptr;
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const int elements = arrayp->rangep()->elementsConst();
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for (int offset = 0; offset < elements; ++offset) {
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@ -591,7 +591,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
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// restore the original decl range here.
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const VNumRange selRange{nodep->declRange().hi() + dtypep->declRange().lo(),
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nodep->declRange().lo() + dtypep->declRange().lo(),
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nodep->declRange().littleEndian()};
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nodep->declRange().ascending()};
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UASSERT_OBJ(dtypep->lo() <= selRange.lo() && selRange.hi() <= dtypep->hi(), nodep,
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"Range check for AstSliceSel must have been finished in V3Width.cpp");
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UINFO(4, "add " << nodep << " for " << refp->varp()->prettyName() << "\n");
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@ -1071,7 +1071,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
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for (SplitNewVar& newvar : vars) {
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int left = newvar.msb();
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int right = newvar.lsb();
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if (basicp->littleEndian()) std::swap(left, right);
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if (basicp->ascending()) std::swap(left, right);
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const std::string name
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= (left == right)
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? varp->name() + "__BRA__" + AstNode::encodeNumber(left) + "__KET__"
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@ -1091,7 +1091,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
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default: UASSERT_OBJ(false, basicp, "Only bit and logic are allowed");
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}
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dtypep->rangep(new AstRange{
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varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->littleEndian()}});
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varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->ascending()}});
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newvar.varp(new AstVar{varp->fileline(), VVarType::VAR, name, dtypep});
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newvar.varp()->propagateAttrFrom(varp);
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newvar.varp()->funcLocal(varp->isFuncLocal() || varp->isFuncReturn());
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@ -101,7 +101,7 @@ private:
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if (lsb == msb) {
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bits += cvtToStr(lsb + bdtypep->lo());
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} else {
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if (bdtypep->littleEndian()) {
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if (bdtypep->ascending()) {
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bits
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+= cvtToStr(lsb + bdtypep->lo()) + ":" + cvtToStr(msb + bdtypep->lo());
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} else {
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@ -858,11 +858,11 @@ private:
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<< std::hex << width);
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}
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// Note width() not set on range; use elementsConst()
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if (nodep->littleEndian() && !VN_IS(nodep->backp(), UnpackArrayDType)
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if (nodep->ascending() && !VN_IS(nodep->backp(), UnpackArrayDType)
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&& !VN_IS(nodep->backp(), Cell)) { // For cells we warn in V3Inst
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nodep->v3warn(LITENDIAN, "Big bit endian vector: left < right of bit range: ["
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<< nodep->leftConst() << ":" << nodep->rightConst()
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<< "]");
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nodep->v3warn(ASCRANGE, "Ascending bit range vector: left < right of bit range: ["
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<< nodep->leftConst() << ":" << nodep->rightConst()
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<< "]");
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}
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}
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}
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@ -1101,18 +1101,18 @@ private:
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// Add subtracted value to get the original range
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const VNumRange declRange{nodep->declRange().hi() + subtracted,
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nodep->declRange().lo() + subtracted,
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nodep->declRange().littleEndian()};
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nodep->declRange().ascending()};
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if ((declRange.hi() > adtypep->declRange().hi())
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|| declRange.lo() < adtypep->declRange().lo()) {
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||||
// Other simulators warn too
|
||||
nodep->v3error("Slice selection index '" << declRange << "'"
|
||||
<< " outside data type's '"
|
||||
<< adtypep->declRange() << "'");
|
||||
} else if ((declRange.littleEndian() != adtypep->declRange().littleEndian())
|
||||
} else if ((declRange.ascending() != adtypep->declRange().ascending())
|
||||
&& declRange.hi() != declRange.lo()) {
|
||||
nodep->v3error("Slice selection '"
|
||||
<< declRange << "'"
|
||||
<< " has backward indexing versus data type's '"
|
||||
<< " has reversed range order versus data type's '"
|
||||
<< adtypep->declRange() << "'");
|
||||
}
|
||||
}
|
||||
@ -6351,9 +6351,8 @@ private:
|
||||
constp->fileline(), lhsDTypep,
|
||||
new AstConst{constp->fileline(), AstConst::WidthedValue{}, 8, 0}};
|
||||
for (int aindex = arrayp->lo(); aindex <= arrayp->hi(); ++aindex) {
|
||||
int cindex = arrayp->declRange().littleEndian()
|
||||
? (arrayp->hi() - aindex)
|
||||
: (aindex - arrayp->lo());
|
||||
int cindex = arrayp->declRange().ascending() ? (arrayp->hi() - aindex)
|
||||
: (aindex - arrayp->lo());
|
||||
V3Number selected{constp, 8};
|
||||
selected.opSel(constp->num(), cindex * 8 + 7, cindex * 8);
|
||||
UINFO(0, " aindex=" << aindex << " cindex=" << cindex
|
||||
@ -6970,7 +6969,7 @@ private:
|
||||
case VAttrType::DIM_LOW: val = !declRange.ranged() ? 0 : declRange.lo(); break;
|
||||
case VAttrType::DIM_RIGHT: val = !declRange.ranged() ? 0 : declRange.right(); break;
|
||||
case VAttrType::DIM_INCREMENT:
|
||||
val = (declRange.ranged() && declRange.littleEndian()) ? -1 : 1;
|
||||
val = (declRange.ranged() && declRange.ascending()) ? -1 : 1;
|
||||
break;
|
||||
case VAttrType::DIM_SIZE: val = !declRange.ranged() ? 0 : declRange.elements(); break;
|
||||
default: nodep->v3fatalSrc("Missing DIM ATTR type case"); break;
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
// Replace SELEXTRACT with SEL
|
||||
// Replace SELBIT with SEL or ARRAYSEL
|
||||
//
|
||||
// This code was once in V3LinkResolve, but little endian bit vectors won't
|
||||
// This code was once in V3LinkResolve, but ascending bit range vectors won't
|
||||
// work that early. It was considered for V3Width and V3Param, but is
|
||||
// fairly ugly both places as the nodes change in too strongly
|
||||
// interconnected ways.
|
||||
@ -162,7 +162,7 @@ private:
|
||||
// vector without range, or 0 lsb is ok, for example a INTEGER x; y = x[21:0];
|
||||
return underp;
|
||||
} else {
|
||||
if (fromRange.littleEndian()) {
|
||||
if (fromRange.ascending()) {
|
||||
// reg [1:3] was swapped to [3:1] (lsbEndianedp==3) and needs a SUB(3,under)
|
||||
return newSubNeg(fromRange.hi(), underp);
|
||||
} else {
|
||||
@ -180,7 +180,7 @@ private:
|
||||
} else {
|
||||
// Need a slice data type, which is an array of the extracted
|
||||
// type, but with (presumably) different size
|
||||
const VNumRange newRange{msb, lsb, nodep->declRange().littleEndian()};
|
||||
const VNumRange newRange{msb, lsb, nodep->declRange().ascending()};
|
||||
AstNodeDType* const vardtypep
|
||||
= new AstPackArrayDType{nodep->fileline(),
|
||||
nodep->subDTypep(), // Need to strip off array reference
|
||||
@ -227,7 +227,7 @@ private:
|
||||
} else if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) {
|
||||
// SELBIT(array, index) -> SEL(array, index*width-of-subindex, width-of-subindex)
|
||||
AstNodeExpr* subp = rhsp;
|
||||
if (fromRange.littleEndian()) {
|
||||
if (fromRange.ascending()) {
|
||||
subp = newSubNeg(fromRange.hi(), subp);
|
||||
} else {
|
||||
subp = newSubNeg(subp, fromRange.lo());
|
||||
@ -375,8 +375,8 @@ private:
|
||||
adtypep,
|
||||
"Array extraction with width miscomputed " << adtypep->width() << "/"
|
||||
<< fromRange.elements());
|
||||
if (fromRange.littleEndian()) {
|
||||
// Below code assumes big bit endian; just works out if we swap
|
||||
if (fromRange.ascending()) {
|
||||
// Below code assumes descending bit range; just works out if we swap
|
||||
const int x = msb;
|
||||
msb = lsb;
|
||||
lsb = x;
|
||||
@ -385,7 +385,7 @@ private:
|
||||
nodep->v3warn(
|
||||
SELRANGE,
|
||||
"[" << msb << ":" << lsb
|
||||
<< "] Range extract has backward bit ordering, perhaps you wanted [" << lsb
|
||||
<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
|
||||
<< ":" << msb << "]");
|
||||
const int x = msb;
|
||||
msb = lsb;
|
||||
@ -405,8 +405,8 @@ private:
|
||||
nodep->replaceWith(newp);
|
||||
VL_DO_DANGLING(pushDeletep(nodep), nodep);
|
||||
} else if (VN_IS(ddtypep, BasicDType)) {
|
||||
if (fromRange.littleEndian()) {
|
||||
// Below code assumes big bit endian; just works out if we swap
|
||||
if (fromRange.ascending()) {
|
||||
// Below code assumes descending bit range; just works out if we swap
|
||||
const int x = msb;
|
||||
msb = lsb;
|
||||
lsb = x;
|
||||
@ -415,7 +415,7 @@ private:
|
||||
nodep->v3warn(
|
||||
SELRANGE,
|
||||
"[" << msb << ":" << lsb
|
||||
<< "] Range extract has backward bit ordering, perhaps you wanted [" << lsb
|
||||
<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
|
||||
<< ":" << msb << "]");
|
||||
const int x = msb;
|
||||
msb = lsb;
|
||||
@ -432,12 +432,12 @@ private:
|
||||
nodep->replaceWith(newp);
|
||||
VL_DO_DANGLING(pushDeletep(nodep), nodep);
|
||||
} else if (VN_IS(ddtypep, NodeUOrStructDType)) {
|
||||
// Classes aren't little endian
|
||||
// Classes don't have an ascending range
|
||||
if (lsb > msb) {
|
||||
nodep->v3warn(
|
||||
SELRANGE,
|
||||
"[" << msb << ":" << lsb
|
||||
<< "] Range extract has backward bit ordering, perhaps you wanted [" << lsb
|
||||
<< "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb
|
||||
<< ":" << msb << "]");
|
||||
const int x = msb;
|
||||
msb = lsb;
|
||||
@ -485,7 +485,8 @@ private:
|
||||
V3Width::widthParamsEdit(nodep->rhsp()); // constifyEdit doesn't ensure widths finished
|
||||
V3Const::constifyEdit(nodep->rhsp()); // May relink pointed to node, ok if not const
|
||||
V3Const::constifyParamsEdit(nodep->thsp()); // May relink pointed to node
|
||||
checkConstantOrReplace(nodep->thsp(), "Width of :+ or :- bit extract isn't a constant");
|
||||
checkConstantOrReplace(nodep->thsp(),
|
||||
"Width of :+ or :- bit slice range isn't a constant");
|
||||
if (debug() >= 9) nodep->dumpTree("- SELPM3: ");
|
||||
// Now replace it with an AstSel
|
||||
AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
|
||||
@ -521,7 +522,7 @@ private:
|
||||
const int32_t msb = VN_IS(nodep, SelPlus) ? rhs + width - 1 : rhs;
|
||||
const int32_t lsb = VN_IS(nodep, SelPlus) ? rhs : rhs - width + 1;
|
||||
AstSliceSel* const newp = new AstSliceSel{
|
||||
nodep->fileline(), fromp, VNumRange{msb, lsb, fromRange.littleEndian()}};
|
||||
nodep->fileline(), fromp, VNumRange{msb, lsb, fromRange.ascending()}};
|
||||
nodep->replaceWith(newp);
|
||||
VL_DO_DANGLING(pushDeletep(nodep), nodep);
|
||||
} else {
|
||||
@ -539,7 +540,7 @@ private:
|
||||
}
|
||||
AstNodeExpr* newlsbp = nullptr;
|
||||
if (VN_IS(nodep, SelPlus)) {
|
||||
if (fromRange.littleEndian()) {
|
||||
if (fromRange.ascending()) {
|
||||
// SELPLUS(from,lsb,width) -> SEL(from, (vector_msb-width+1)-sel, width)
|
||||
newlsbp = newSubNeg((fromRange.hi() - width + 1), rhsp);
|
||||
} else {
|
||||
@ -547,7 +548,7 @@ private:
|
||||
newlsbp = newSubNeg(rhsp, fromRange.lo());
|
||||
}
|
||||
} else if (VN_IS(nodep, SelMinus)) {
|
||||
if (fromRange.littleEndian()) {
|
||||
if (fromRange.ascending()) {
|
||||
// SELMINUS(from,msb,width) -> SEL(from, msb-[bit])
|
||||
newlsbp = newSubNeg(fromRange.hi(), rhsp);
|
||||
} else {
|
||||
|
||||
@ -1,16 +1,16 @@
|
||||
%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]'
|
||||
%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]'
|
||||
: ... In instance t
|
||||
17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
|
||||
| ^
|
||||
%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]'
|
||||
%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]'
|
||||
: ... In instance t
|
||||
18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
|
||||
| ^
|
||||
%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has backward indexing versus data type's '[6:3]'
|
||||
%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]'
|
||||
: ... In instance t
|
||||
19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
|
||||
| ^
|
||||
%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has backward indexing versus data type's '[3:6]'
|
||||
%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]'
|
||||
: ... In instance t
|
||||
20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
|
||||
| ^
|
||||
|
||||
@ -12,27 +12,27 @@ typedef struct packed {
|
||||
} tb_t;
|
||||
|
||||
typedef struct packed {
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
logic [0:7] a;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
} tl_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [7:0] bb;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
tb_t [0:1] cbl;
|
||||
tb_t [1:0] cbb;
|
||||
tl_t [0:1] cll;
|
||||
tl_t [1:0] clb;
|
||||
logic [0:7] dl;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
} t2;
|
||||
|
||||
logic [2:0][31:0] test2l;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
logic [0:2][31:0] test2b;
|
||||
logic [0:2][31:0] test1b;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
logic [2:0][31:0] test1l;
|
||||
|
||||
module t;
|
||||
|
||||
@ -19,10 +19,10 @@ module t (/*AUTOARG*/
|
||||
localparam WC = 8;
|
||||
|
||||
// 2D packed arrays
|
||||
logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array
|
||||
/* verilator lint_off LITENDIAN */
|
||||
logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array
|
||||
/* verilator lint_on LITENDIAN */
|
||||
logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array
|
||||
/* verilator lint_off ASCRANGE */
|
||||
logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
logic [1:0] array_unpk [3:2][1:0];
|
||||
|
||||
@ -83,84 +83,84 @@ module t (/*AUTOARG*/
|
||||
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
|
||||
`endif
|
||||
if (cnt[30:4]==1) begin
|
||||
// big endian
|
||||
// descending range
|
||||
if (slc==0) begin
|
||||
// full array
|
||||
`checkh($dimensions (array_bg), 3);
|
||||
`checkh($bits (array_bg), WA*WB*WC);
|
||||
`checkh($dimensions (array_dsc), 3);
|
||||
`checkh($bits (array_dsc), WA*WB*WC);
|
||||
if ((dim>=1)&&(dim<=3)) begin
|
||||
`checkh($left (array_bg, dim), wdt+1);
|
||||
`checkh($right (array_bg, dim), 2 );
|
||||
`checkh($low (array_bg, dim), 2 );
|
||||
`checkh($high (array_bg, dim), wdt+1);
|
||||
`checkh($increment (array_bg, dim), 1 );
|
||||
`checkh($size (array_bg, dim), wdt );
|
||||
`checkh($left (array_dsc, dim), wdt+1);
|
||||
`checkh($right (array_dsc, dim), 2 );
|
||||
`checkh($low (array_dsc, dim), 2 );
|
||||
`checkh($high (array_dsc, dim), wdt+1);
|
||||
`checkh($increment (array_dsc, dim), 1 );
|
||||
`checkh($size (array_dsc, dim), wdt );
|
||||
end
|
||||
end else if (slc==1) begin
|
||||
// single array element
|
||||
`checkh($dimensions (array_bg[2]), 2);
|
||||
`checkh($bits (array_bg[2]), WB*WC);
|
||||
`checkh($dimensions (array_dsc[2]), 2);
|
||||
`checkh($bits (array_dsc[2]), WB*WC);
|
||||
if ((dim>=2)&&(dim<=3)) begin
|
||||
`checkh($left (array_bg[2], dim-1), wdt+1);
|
||||
`checkh($right (array_bg[2], dim-1), 2 );
|
||||
`checkh($low (array_bg[2], dim-1), 2 );
|
||||
`checkh($high (array_bg[2], dim-1), wdt+1);
|
||||
`checkh($increment (array_bg[2], dim-1), 1 );
|
||||
`checkh($size (array_bg[2], dim-1), wdt );
|
||||
`checkh($left (array_dsc[2], dim-1), wdt+1);
|
||||
`checkh($right (array_dsc[2], dim-1), 2 );
|
||||
`checkh($low (array_dsc[2], dim-1), 2 );
|
||||
`checkh($high (array_dsc[2], dim-1), wdt+1);
|
||||
`checkh($increment (array_dsc[2], dim-1), 1 );
|
||||
`checkh($size (array_dsc[2], dim-1), wdt );
|
||||
end
|
||||
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
||||
end else if (slc==2) begin
|
||||
// half array
|
||||
`checkh($dimensions (array_bg[WA/2+1:2]), 3);
|
||||
`checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC);
|
||||
`checkh($dimensions (array_dsc[WA/2+1:2]), 3);
|
||||
`checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC);
|
||||
if ((dim>=1)&&(dim<=3)) begin
|
||||
`checkh($left (array_bg[WA/2+1:2], dim), wdt+1);
|
||||
`checkh($right (array_bg[WA/2+1:2], dim), 2 );
|
||||
`checkh($low (array_bg[WA/2+1:2], dim), 2 );
|
||||
`checkh($high (array_bg[WA/2+1:2], dim), wdt+1);
|
||||
`checkh($increment (array_bg[WA/2+1:2], dim), 1 );
|
||||
`checkh($size (array_bg[WA/2+1:2], dim), wdt);
|
||||
`checkh($left (array_dsc[WA/2+1:2], dim), wdt+1);
|
||||
`checkh($right (array_dsc[WA/2+1:2], dim), 2 );
|
||||
`checkh($low (array_dsc[WA/2+1:2], dim), 2 );
|
||||
`checkh($high (array_dsc[WA/2+1:2], dim), wdt+1);
|
||||
`checkh($increment (array_dsc[WA/2+1:2], dim), 1 );
|
||||
`checkh($size (array_dsc[WA/2+1:2], dim), wdt);
|
||||
end
|
||||
`endif
|
||||
end
|
||||
end else if (cnt[30:4]==2) begin
|
||||
// little endian
|
||||
// ascending range
|
||||
if (slc==0) begin
|
||||
// full array
|
||||
`checkh($dimensions (array_lt), 3);
|
||||
`checkh($bits (array_lt), WA*WB*WC);
|
||||
`checkh($dimensions (array_asc), 3);
|
||||
`checkh($bits (array_asc), WA*WB*WC);
|
||||
if ((dim>=1)&&(dim<=3)) begin
|
||||
`checkh($left (array_lt, dim), 2 );
|
||||
`checkh($right (array_lt, dim), wdt+1);
|
||||
`checkh($low (array_lt, dim), 2 );
|
||||
`checkh($high (array_lt, dim), wdt+1);
|
||||
`checkh($increment (array_lt, dim), -1 );
|
||||
`checkh($size (array_lt, dim), wdt );
|
||||
`checkh($left (array_asc, dim), 2 );
|
||||
`checkh($right (array_asc, dim), wdt+1);
|
||||
`checkh($low (array_asc, dim), 2 );
|
||||
`checkh($high (array_asc, dim), wdt+1);
|
||||
`checkh($increment (array_asc, dim), -1 );
|
||||
`checkh($size (array_asc, dim), wdt );
|
||||
end
|
||||
end else if (slc==1) begin
|
||||
// single array element
|
||||
`checkh($dimensions (array_lt[2]), 2);
|
||||
`checkh($bits (array_lt[2]), WB*WC);
|
||||
`checkh($dimensions (array_asc[2]), 2);
|
||||
`checkh($bits (array_asc[2]), WB*WC);
|
||||
if ((dim>=2)&&(dim<=3)) begin
|
||||
`checkh($left (array_lt[2], dim-1), 2 );
|
||||
`checkh($right (array_lt[2], dim-1), wdt+1);
|
||||
`checkh($low (array_lt[2], dim-1), 2 );
|
||||
`checkh($high (array_lt[2], dim-1), wdt+1);
|
||||
`checkh($increment (array_lt[2], dim-1), -1 );
|
||||
`checkh($size (array_lt[2], dim-1), wdt );
|
||||
`checkh($left (array_asc[2], dim-1), 2 );
|
||||
`checkh($right (array_asc[2], dim-1), wdt+1);
|
||||
`checkh($low (array_asc[2], dim-1), 2 );
|
||||
`checkh($high (array_asc[2], dim-1), wdt+1);
|
||||
`checkh($increment (array_asc[2], dim-1), -1 );
|
||||
`checkh($size (array_asc[2], dim-1), wdt );
|
||||
end
|
||||
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
||||
end else if (slc==2) begin
|
||||
// half array
|
||||
`checkh($dimensions (array_lt[2:WA/2+1]), 3);
|
||||
`checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC);
|
||||
`checkh($dimensions (array_asc[2:WA/2+1]), 3);
|
||||
`checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC);
|
||||
if ((dim>=1)&&(dim<=3)) begin
|
||||
`checkh($left (array_lt[2:WA/2+1], dim), 2 );
|
||||
`checkh($right (array_lt[2:WA/2+1], dim), wdt+1);
|
||||
`checkh($low (array_lt[2:WA/2+1], dim), 2 );
|
||||
`checkh($high (array_lt[2:WA/2+1], dim), wdt+1);
|
||||
`checkh($increment (array_lt[2:WA/2+1], dim), -1 );
|
||||
`checkh($size (array_lt[2:WA/2+1], dim), wdt );
|
||||
`checkh($left (array_asc[2:WA/2+1], dim), 2 );
|
||||
`checkh($right (array_asc[2:WA/2+1], dim), wdt+1);
|
||||
`checkh($low (array_asc[2:WA/2+1], dim), 2 );
|
||||
`checkh($high (array_asc[2:WA/2+1], dim), wdt+1);
|
||||
`checkh($increment (array_asc[2:WA/2+1], dim), -1 );
|
||||
`checkh($size (array_asc[2:WA/2+1], dim), wdt );
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
@ -18,10 +18,10 @@ module t (/*AUTOARG*/
|
||||
localparam NO = 10; // number of access events
|
||||
|
||||
// 2D packed arrays
|
||||
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
|
||||
/* verilator lint_off LITENDIAN */
|
||||
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
|
||||
/* verilator lint_on LITENDIAN */
|
||||
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
|
||||
/* verilator lint_off ASCRANGE */
|
||||
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
integer cnt = 0;
|
||||
|
||||
@ -41,108 +41,108 @@ module t (/*AUTOARG*/
|
||||
$finish;
|
||||
end
|
||||
|
||||
// big endian
|
||||
// descending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaaults (all bits to 0)
|
||||
if (cnt[30:2]==0) array_bg <= '0;
|
||||
else if (cnt[30:2]==1) array_bg <= '0;
|
||||
else if (cnt[30:2]==2) array_bg <= '0;
|
||||
else if (cnt[30:2]==3) array_bg <= '0;
|
||||
else if (cnt[30:2]==4) array_bg <= '0;
|
||||
else if (cnt[30:2]==5) array_bg <= '0;
|
||||
else if (cnt[30:2]==6) array_bg <= '0;
|
||||
else if (cnt[30:2]==7) array_bg <= '0;
|
||||
else if (cnt[30:2]==8) array_bg <= '0;
|
||||
else if (cnt[30:2]==9) array_bg <= '0;
|
||||
if (cnt[30:2]==0) array_dsc <= '0;
|
||||
else if (cnt[30:2]==1) array_dsc <= '0;
|
||||
else if (cnt[30:2]==2) array_dsc <= '0;
|
||||
else if (cnt[30:2]==3) array_dsc <= '0;
|
||||
else if (cnt[30:2]==4) array_dsc <= '0;
|
||||
else if (cnt[30:2]==5) array_dsc <= '0;
|
||||
else if (cnt[30:2]==6) array_dsc <= '0;
|
||||
else if (cnt[30:2]==7) array_dsc <= '0;
|
||||
else if (cnt[30:2]==8) array_dsc <= '0;
|
||||
else if (cnt[30:2]==9) array_dsc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write value to array
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// check array value
|
||||
if (cnt[30:2]==0) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (array_bg !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (array_bg !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (array_bg !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==8) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]==9) begin if (array_bg !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
end else if (cnt[1:0]==2'd3) begin
|
||||
// read value from array (not a very good test for now)
|
||||
if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
end
|
||||
|
||||
// little endian
|
||||
// ascending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaaults (all bits to 0)
|
||||
if (cnt[30:2]==0) array_lt <= '0;
|
||||
else if (cnt[30:2]==1) array_lt <= '0;
|
||||
else if (cnt[30:2]==2) array_lt <= '0;
|
||||
else if (cnt[30:2]==3) array_lt <= '0;
|
||||
else if (cnt[30:2]==4) array_lt <= '0;
|
||||
else if (cnt[30:2]==5) array_lt <= '0;
|
||||
else if (cnt[30:2]==6) array_lt <= '0;
|
||||
else if (cnt[30:2]==7) array_lt <= '0;
|
||||
else if (cnt[30:2]==8) array_lt <= '0;
|
||||
else if (cnt[30:2]==9) array_lt <= '0;
|
||||
if (cnt[30:2]==0) array_asc <= '0;
|
||||
else if (cnt[30:2]==1) array_asc <= '0;
|
||||
else if (cnt[30:2]==2) array_asc <= '0;
|
||||
else if (cnt[30:2]==3) array_asc <= '0;
|
||||
else if (cnt[30:2]==4) array_asc <= '0;
|
||||
else if (cnt[30:2]==5) array_asc <= '0;
|
||||
else if (cnt[30:2]==6) array_asc <= '0;
|
||||
else if (cnt[30:2]==7) array_asc <= '0;
|
||||
else if (cnt[30:2]==8) array_asc <= '0;
|
||||
else if (cnt[30:2]==9) array_asc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write value to array
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
|
||||
else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}};
|
||||
else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
|
||||
else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}};
|
||||
else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// check array value
|
||||
if (cnt[30:2]==0) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (array_lt !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (array_lt !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (array_lt !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==7) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==8) begin if (array_lt !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==9) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_lt); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end
|
||||
end else if (cnt[1:0]==2'd3) begin
|
||||
// read value from array (not a very good test for now)
|
||||
if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||
|
||||
input clk;
|
||||
|
||||
logic [1:0] [3:0] [3:0] array_simp; // big endian array
|
||||
logic [1:0] [3:0] [3:0] array_simp; // descending range array
|
||||
|
||||
logic [3:0] array_oned;
|
||||
|
||||
@ -61,10 +61,10 @@ module t (/*AUTOARG*/
|
||||
localparam NO = 11; // number of access events
|
||||
|
||||
// 2D packed arrays
|
||||
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
|
||||
/* verilator lint_off LITENDIAN */
|
||||
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
|
||||
/* verilator lint_on LITENDIAN */
|
||||
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
|
||||
/* verilator lint_off ASCRANGE */
|
||||
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
integer cnt = 0;
|
||||
|
||||
@ -80,74 +80,74 @@ module t (/*AUTOARG*/
|
||||
$finish;
|
||||
end
|
||||
|
||||
// big endian
|
||||
// descending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaults (all bits 1'b0)
|
||||
if (cnt[30:2]== 0) array_bg <= '0;
|
||||
else if (cnt[30:2]== 1) array_bg <= '0;
|
||||
else if (cnt[30:2]== 2) array_bg <= '0;
|
||||
else if (cnt[30:2]== 3) array_bg <= '0;
|
||||
else if (cnt[30:2]== 4) array_bg <= '0;
|
||||
else if (cnt[30:2]== 5) array_bg <= '0;
|
||||
else if (cnt[30:2]== 6) array_bg <= '0;
|
||||
else if (cnt[30:2]== 7) array_bg <= '0;
|
||||
else if (cnt[30:2]== 8) array_bg <= '0;
|
||||
else if (cnt[30:2]== 9) array_bg <= '0;
|
||||
else if (cnt[30:2]==10) array_bg <= '0;
|
||||
if (cnt[30:2]== 0) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 1) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 2) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 3) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 4) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 5) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 6) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 7) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 8) array_dsc <= '0;
|
||||
else if (cnt[30:2]== 9) array_dsc <= '0;
|
||||
else if (cnt[30:2]==10) array_dsc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write data into whole or part of the array using literals
|
||||
if (cnt[30:2]== 0) begin end
|
||||
else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 };
|
||||
else if (cnt[30:2]== 2) array_bg <= '{default:13};
|
||||
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
|
||||
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
|
||||
else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
|
||||
else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
|
||||
else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 };
|
||||
else if (cnt[30:2]== 2) array_dsc <= '{default:13};
|
||||
else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7};
|
||||
else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13};
|
||||
else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }};
|
||||
else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// chack array agains expected value
|
||||
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
|
||||
else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end
|
||||
if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end
|
||||
else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end
|
||||
end
|
||||
|
||||
// little endian
|
||||
// ascending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaults (all bits 1'b0)
|
||||
if (cnt[30:2]== 0) array_lt <= '0;
|
||||
else if (cnt[30:2]== 1) array_lt <= '0;
|
||||
else if (cnt[30:2]== 2) array_lt <= '0;
|
||||
else if (cnt[30:2]== 3) array_lt <= '0;
|
||||
else if (cnt[30:2]== 4) array_lt <= '0;
|
||||
else if (cnt[30:2]== 5) array_lt <= '0;
|
||||
else if (cnt[30:2]== 6) array_lt <= '0;
|
||||
else if (cnt[30:2]== 7) array_lt <= '0;
|
||||
else if (cnt[30:2]== 8) array_lt <= '0;
|
||||
else if (cnt[30:2]== 9) array_lt <= '0;
|
||||
else if (cnt[30:2]==10) array_lt <= '0;
|
||||
if (cnt[30:2]== 0) array_asc <= '0;
|
||||
else if (cnt[30:2]== 1) array_asc <= '0;
|
||||
else if (cnt[30:2]== 2) array_asc <= '0;
|
||||
else if (cnt[30:2]== 3) array_asc <= '0;
|
||||
else if (cnt[30:2]== 4) array_asc <= '0;
|
||||
else if (cnt[30:2]== 5) array_asc <= '0;
|
||||
else if (cnt[30:2]== 6) array_asc <= '0;
|
||||
else if (cnt[30:2]== 7) array_asc <= '0;
|
||||
else if (cnt[30:2]== 8) array_asc <= '0;
|
||||
else if (cnt[30:2]== 9) array_asc <= '0;
|
||||
else if (cnt[30:2]==10) array_asc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write data into whole or part of the array using literals
|
||||
if (cnt[30:2]== 0) begin end
|
||||
else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 };
|
||||
else if (cnt[30:2]== 2) array_lt <= '{default:13};
|
||||
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
|
||||
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
|
||||
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
|
||||
else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
|
||||
else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 };
|
||||
else if (cnt[30:2]== 2) array_asc <= '{default:13};
|
||||
else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7};
|
||||
else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13};
|
||||
else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }};
|
||||
else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// chack array agains expected value
|
||||
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
|
||||
else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end
|
||||
if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end
|
||||
else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
logic [3:0] array_simp [1:0] [3:0]; // big endian array
|
||||
logic [3:0] array_simp [1:0] [3:0]; // descending range array
|
||||
|
||||
int irep[1:2][1:6];
|
||||
|
||||
|
||||
@ -40,9 +40,9 @@ module array_test
|
||||
|
||||
input clk;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [7:0] a [LEFT:RIGHT];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
typedef reg [7:0] r_t;
|
||||
|
||||
|
||||
@ -12,9 +12,9 @@ module t (/*AUTOARG*/
|
||||
input clk;
|
||||
|
||||
integer cyc = 0;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
logic arrd [0:1] = '{ 1'b1, 1'b0 };
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
logic y0, y1;
|
||||
logic localbkw [1:0];
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
/* verilator lint_off LITENDIAN */
|
||||
/* verilator lint_off ASCRANGE */
|
||||
module some_module (
|
||||
input wrclk
|
||||
);
|
||||
|
||||
@ -31,7 +31,7 @@ foreach my $s (
|
||||
'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error
|
||||
# Not yet analyzed
|
||||
' is not an in/out/inout/param/interface: ',
|
||||
'Big endian instance range connecting to ',
|
||||
'Descending instance range connecting to ',
|
||||
' loading non-variable',
|
||||
'--pipe-filter protocol error, unexpected: ',
|
||||
'/*verilator sformat*/ can only be applied to last argument of ',
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
// verilator lint_off WIDTH
|
||||
|
||||
reg [63:0] sum; // Checked not in objects
|
||||
|
||||
@ -20,7 +20,7 @@ module t (/*AUTOARG*/
|
||||
|
||||
assign inc = 4'b0001;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
|
||||
COUNTER UCOUNTER1[N-1:0]
|
||||
(
|
||||
|
||||
@ -22,13 +22,13 @@ module t ();
|
||||
|
||||
wire [2:0] X = 3'b110;
|
||||
|
||||
// Should not cause LITENDIAN warning, as no harm in array selections.
|
||||
// verilator lint_on LITENDIAN
|
||||
// Should not cause ASCRANGE warning, as no harm in array selections.
|
||||
// verilator lint_on ASCRANGE
|
||||
foo_intf foo1 [N] (.x(1'b1));
|
||||
foo_subm sub1 [N] (.x(1'b1));
|
||||
|
||||
// Will cause LITENDIAN warning?
|
||||
// verilator lint_off LITENDIAN
|
||||
// Will cause ASCRANGE warning?
|
||||
// verilator lint_off ASCRANGE
|
||||
foo_intf foos [N] (.x(X));
|
||||
foo_intf fool [1:3] (.x(X));
|
||||
foo_intf foom [3:1] (.x(X));
|
||||
|
||||
@ -1,19 +1,19 @@
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Big endian instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:26:26: Ascending instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
26 | foo_intf foos [N] (.x(X));
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/LITENDIAN?v=latest
|
||||
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Big endian instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/ASCRANGE?v=latest
|
||||
... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message.
|
||||
%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:27:28: Ascending instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
27 | foo_intf fool [1:3] (.x(X));
|
||||
| ^
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Big endian instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:30:26: Ascending instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
30 | foo_subm subs [N] (.x(X));
|
||||
| ^
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Big endian instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:31:28: Ascending instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
31 | foo_subm subl [1:3] (.x(X));
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
||||
@ -22,7 +22,7 @@ module t ();
|
||||
|
||||
wire [2:0] X = 3'b110;
|
||||
|
||||
// Will cause LITENDIAN warning?
|
||||
// Will cause ASCRANGE warning?
|
||||
foo_intf foos [N] (.x(X)); // bad
|
||||
foo_intf fool [1:3] (.x(X)); // bad
|
||||
foo_intf foom [3:1] (.x(X)); // ok
|
||||
|
||||
@ -57,10 +57,10 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
|
||||
logic [128:0] s129_out;
|
||||
logic [3:0] [31:0] s4x32_in;
|
||||
logic [3:0] [31:0] s4x32_out;
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
logic [0:15] s6x16up_in[0:1][2:0];
|
||||
logic [0:15] s6x16up_out[0:1][2:0];
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
logic [15:0] s8x16up_in[1:0][0:3];
|
||||
logic [15:0] s8x16up_out[1:0][0:3];
|
||||
logic [15:0] s8x16up_3d_in[1:0][0:1][0:1];
|
||||
|
||||
@ -27,10 +27,10 @@ module secret #(parameter GATED_CLK = 0)
|
||||
output logic [128:0] s129_out,
|
||||
input [3:0] [31:0] s4x32_in,
|
||||
output logic [3:0] [31:0] s4x32_out,
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
input [0:15] s6x16up_in[0:1][2:0],
|
||||
output logic [0:15] s6x16up_out[0:1][2:0],
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
input [15:0] s8x16up_in[1:0][0:3],
|
||||
output logic [15:0] s8x16up_out[1:0][0:3],
|
||||
input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
|
||||
|
||||
@ -45,7 +45,7 @@ module t;
|
||||
// verilator lint_off INITIALDLY
|
||||
// verilator lint_off INSECURE
|
||||
// verilator lint_off LATCH
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
// verilator lint_off MODDUP
|
||||
// verilator lint_off MULTIDRIVEN
|
||||
// verilator lint_off MULTITOP
|
||||
|
||||
@ -89,9 +89,9 @@ module fifo (/*AUTOARG*/
|
||||
reg [65:0] outData;
|
||||
|
||||
// verilator lint_off VARHIDDEN
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [65:0] fifo[0:fifoDepth-1];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
// verilator lint_on VARHIDDEN
|
||||
|
||||
//reg [65:0] temp;
|
||||
|
||||
@ -12,13 +12,13 @@ module t (/*AUTOARG*/
|
||||
input clk;
|
||||
integer _mode; initial _mode = 0;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
|
||||
reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
|
||||
reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
|
||||
reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
|
||||
reg [34:0] vec_wide;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
reg [31:0] wrd0 [15:0];
|
||||
wire [3:0] sel = 4'h3;
|
||||
|
||||
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||
|
||||
input clk;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
// verilator lint_off BLKANDNBLK
|
||||
// 3 3 4
|
||||
reg [71:0] memw [2:0][1:3][5:2];
|
||||
@ -29,7 +29,7 @@ module t (/*AUTOARG*/
|
||||
|
||||
integer imem[2:0][1:3];
|
||||
reg [2:0] cstyle[2];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
initial begin
|
||||
for (i0=0; i0<3; i0=i0+1) begin
|
||||
|
||||
@ -11,10 +11,10 @@ module t (/*AUTOARG*/
|
||||
|
||||
input clk;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
wire [7:0] array [2:0][1:3];
|
||||
wire [7:0] arrayNoColon [2][3];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
integer cyc; initial cyc = 0;
|
||||
integer i0,i1,i2;
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Big bit endian vector: left < right of bit range: [0:1]
|
||||
: ... In instance t
|
||||
8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3;
|
||||
%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:8: Ascending bit range vector: left < right of bit range: [0:1]
|
||||
: ... In instance t
|
||||
8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/LITENDIAN?v=latest
|
||||
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
|
||||
%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Big bit endian vector: left < right of bit range: [0:3]
|
||||
: ... In instance t
|
||||
8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/ASCRANGE?v=latest
|
||||
... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message.
|
||||
%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:107: Ascending bit range vector: left < right of bit range: [0:3]
|
||||
: ... In instance t
|
||||
8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3;
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
module t;
|
||||
// Test turning on and off a message on the same line; only middle reg shouldn't warn
|
||||
reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3;
|
||||
reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3;
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
@ -44,9 +44,9 @@ module t
|
||||
logic [N-1:0] a_in;
|
||||
logic [N-1:0] a_out;
|
||||
logic [N-1:0] ack_out;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
a_if #(.PARAM(1)) tl_intf [N] ();
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
intf_source source(a_in, tl_intf);
|
||||
intf_sink sink(a_out, tl_intf);
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
parameter N = 4;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
|
||||
interface a_if #(parameter PARAM = 0) ();
|
||||
logic long_name;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
// used in the test module to set the value of MSB. A number of warnings and
|
||||
// errors follow, starting with:
|
||||
//
|
||||
// %Warning-LITENDIAN: t/t_param_module.v:42: Big bit endian vector: MSB
|
||||
// %Warning-ASCRANGE: t/t_param_module.v:42: Ascending bit range vector: MSB
|
||||
// < LSB of bit range: -17:0
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use, without
|
||||
|
||||
@ -21,9 +21,9 @@ module t (/*AUTOARG*/
|
||||
parameter DWORDS_LOG2 = 7;
|
||||
parameter DWORDS = (1<<DWORDS_LOG2);
|
||||
parameter DBYTES=DBITS/8;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [DBITS-1:0] mem [0:DWORDS-1];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
integer i;
|
||||
|
||||
|
||||
21
test_regress/t/t_select_ascending.pl
Executable file
21
test_regress/t/t_select_ascending.pl
Executable file
@ -0,0 +1,21 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
compile(
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
75
test_regress/t/t_select_ascending.v
Normal file
75
test_regress/t/t_select_ascending.v
Normal file
@ -0,0 +1,75 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2009 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc = 0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// verilator lint_off ASCRANGE
|
||||
wire [10:41] sel2 = crc[31:0];
|
||||
wire [10:100] sel3 = {crc[26:0],crc};
|
||||
|
||||
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
|
||||
wire [3:0] out21 = sel2[13 : 16];
|
||||
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
|
||||
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
|
||||
|
||||
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
|
||||
wire [3:0] out31 = sel3[13 : 16];
|
||||
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
|
||||
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
|
||||
|
||||
reg [19:50] sel1;
|
||||
initial begin
|
||||
// Path clearing
|
||||
// 122333445
|
||||
// 826048260
|
||||
sel1 = 32'h12345678;
|
||||
if (sel1 != 32'h12345678) $stop;
|
||||
if (sel1[47 : 50] != 4'h8) $stop;
|
||||
if (sel1[31 : 34] != 4'h4) $stop;
|
||||
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
|
||||
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
|
||||
end
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33);
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
`define EXPECTED_SUM 64'h28bf65439eb12c00
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,10 +1,10 @@
|
||||
%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Big bit endian vector: left < right of bit range: [0:22]
|
||||
: ... In instance t
|
||||
%Warning-ASCRANGE: t/t_select_bad_msb.v:12:8: Ascending bit range vector: left < right of bit range: [0:22]
|
||||
: ... In instance t
|
||||
12 | reg [0:22] backwd;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/LITENDIAN?v=latest
|
||||
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
|
||||
%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
|
||||
... For warning description see https://verilator.org/warn/ASCRANGE?v=latest
|
||||
... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message.
|
||||
%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Slice range has ascending bit ordering, perhaps you wanted [4:1]
|
||||
: ... In instance t
|
||||
16 | sel2 = mi[1:4];
|
||||
| ^
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
: ... In instance t
|
||||
22 | sel2 = mi[44 +: nonconst];
|
||||
| ^~~~~~~~
|
||||
%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit extract isn't a constant
|
||||
%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit slice range isn't a constant
|
||||
: ... In instance t
|
||||
22 | sel2 = mi[44 +: nonconst];
|
||||
| ^~~~~~~~
|
||||
|
||||
@ -10,7 +10,7 @@ module t (/*AUTOARG*/
|
||||
);
|
||||
input clk;
|
||||
|
||||
// No endian warning here
|
||||
// No ascending range warning here
|
||||
reg [7:0] pack [3:0];
|
||||
|
||||
initial begin
|
||||
|
||||
@ -175,9 +175,9 @@ module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEP
|
||||
(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
|
||||
|
||||
localparam OFFSET = -2;
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/;
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
|
||||
generate
|
||||
for(genvar i = 0; i < DEPTH; ++i) begin
|
||||
@ -201,9 +201,9 @@ module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**
|
||||
(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
|
||||
|
||||
localparam OFFSET = -2;
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/;
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
|
||||
generate
|
||||
for(genvar i = 0; i < DEPTH; ++i) begin
|
||||
@ -245,9 +245,9 @@ endmodule
|
||||
module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
|
||||
(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
|
||||
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/;
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
|
||||
generate
|
||||
for(genvar i = 0; i < DEPTH; ++i) begin
|
||||
@ -267,10 +267,10 @@ endmodule
|
||||
|
||||
module var_decl_with_init();
|
||||
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
logic [-1:30] var0 /* verilator split_var */ = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7};
|
||||
logic [-1:30] var2 /* verilator split_var */;
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
logic [30:-1] var1 /* verilator split_var */ = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7};
|
||||
logic [30:-1] var3 /* verilator split_var */;
|
||||
|
||||
@ -290,9 +290,9 @@ module t_array_rev(clk); // from t_array_rev.v
|
||||
input clk;
|
||||
|
||||
integer cyc = 0;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
logic arrd [0:1] /*verilator split_var*/ = '{ 1'b1, 1'b0 };
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
logic y0, y1;
|
||||
logic localbkw [1:0]/*verilator split_var*/ ;
|
||||
|
||||
@ -442,11 +442,11 @@ module t(/*AUTOARG*/ clk);
|
||||
t_array_rev i_t_array_rev(clk);
|
||||
|
||||
assign in = 8'b10001110;
|
||||
/*verilator lint_off LITENDIAN*/
|
||||
/*verilator lint_off ASCRANGE*/
|
||||
logic [7:0] [7:0] expc
|
||||
= {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
|
||||
8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
|
||||
/*verilator lint_on LITENDIAN*/
|
||||
/*verilator lint_on ASCRANGE*/
|
||||
always @(posedge clk) begin : always_block
|
||||
automatic bit failed = 0;
|
||||
$display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]);
|
||||
|
||||
@ -17,15 +17,15 @@ module t (/*AUTOARG*/
|
||||
logic [1:0] e1;
|
||||
logic [3:0] e2;
|
||||
logic [7:0] e3;
|
||||
} struct_bg; // big endian structure
|
||||
/* verilator lint_off LITENDIAN */
|
||||
} struct_dsc; // descendng range structure
|
||||
/* verilator lint_off ASCRANGE */
|
||||
struct packed {
|
||||
logic e0;
|
||||
logic [0:1] e1;
|
||||
logic [0:3] e2;
|
||||
logic [0:7] e3;
|
||||
} struct_lt; // little endian structure
|
||||
/* verilator lint_on LITENDIAN */
|
||||
} struct_asc; // ascending range structure
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
integer cnt = 0;
|
||||
|
||||
@ -44,20 +44,20 @@ module t (/*AUTOARG*/
|
||||
|
||||
always @ (posedge clk)
|
||||
if (cnt==1) begin
|
||||
// big endian
|
||||
if ($bits (struct_bg ) != 15) $stop;
|
||||
if ($bits (struct_bg.e0) != 1) $stop;
|
||||
if ($bits (struct_bg.e1) != 2) $stop;
|
||||
if ($bits (struct_bg.e2) != 4) $stop;
|
||||
if ($bits (struct_bg.e3) != 8) $stop;
|
||||
if ($increment (struct_bg, 1) != 1) $stop;
|
||||
// little endian
|
||||
if ($bits (struct_lt ) != 15) $stop;
|
||||
if ($bits (struct_lt.e0) != 1) $stop;
|
||||
if ($bits (struct_lt.e1) != 2) $stop;
|
||||
if ($bits (struct_lt.e2) != 4) $stop;
|
||||
if ($bits (struct_lt.e3) != 8) $stop;
|
||||
if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered
|
||||
// descending range
|
||||
if ($bits (struct_dsc ) != 15) $stop;
|
||||
if ($bits (struct_dsc.e0) != 1) $stop;
|
||||
if ($bits (struct_dsc.e1) != 2) $stop;
|
||||
if ($bits (struct_dsc.e2) != 4) $stop;
|
||||
if ($bits (struct_dsc.e3) != 8) $stop;
|
||||
if ($increment (struct_dsc, 1) != 1) $stop;
|
||||
// ascending range
|
||||
if ($bits (struct_asc ) != 15) $stop;
|
||||
if ($bits (struct_asc.e0) != 1) $stop;
|
||||
if ($bits (struct_asc.e1) != 2) $stop;
|
||||
if ($bits (struct_asc.e2) != 4) $stop;
|
||||
if ($bits (struct_asc.e3) != 8) $stop;
|
||||
if ($increment (struct_asc, 1) != 1) $stop; // Structure itself always big numbered
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -19,17 +19,17 @@ module t (/*AUTOARG*/
|
||||
logic [1:0] e1;
|
||||
logic [3:0] e2;
|
||||
logic [7:0] e3;
|
||||
} struct_bg; // big endian structure
|
||||
/* verilator lint_off LITENDIAN */
|
||||
} struct_dsc; // descending range structure
|
||||
/* verilator lint_off ASCRANGE */
|
||||
struct packed {
|
||||
logic e0;
|
||||
logic [0:1] e1;
|
||||
logic [0:3] e2;
|
||||
logic [0:7] e3;
|
||||
} struct_lt; // little endian structure
|
||||
/* verilator lint_on LITENDIAN */
|
||||
} struct_asc; // ascending range structure
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
localparam WS = 15; // $bits(struct_bg)
|
||||
localparam WS = 15; // $bits(struct_dsc)
|
||||
|
||||
integer cnt = 0;
|
||||
|
||||
@ -46,70 +46,70 @@ module t (/*AUTOARG*/
|
||||
$finish;
|
||||
end
|
||||
|
||||
// big endian
|
||||
// descending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaults (all bits 1'b0)
|
||||
if (cnt[30:2]==0) struct_bg <= '0;
|
||||
else if (cnt[30:2]==1) struct_bg <= '0;
|
||||
else if (cnt[30:2]==2) struct_bg <= '0;
|
||||
else if (cnt[30:2]==3) struct_bg <= '0;
|
||||
else if (cnt[30:2]==4) struct_bg <= '0;
|
||||
else if (cnt[30:2]==5) struct_bg <= '0;
|
||||
else if (cnt[30:2]==6) struct_bg <= '0;
|
||||
if (cnt[30:2]==0) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==1) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==2) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==3) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==4) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==5) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==6) struct_dsc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write data into whole or part of the array using literals
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3};
|
||||
else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4};
|
||||
else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0};
|
||||
else if (cnt[30:2]==1) struct_dsc <= '{0 ,1 , 2, 3};
|
||||
else if (cnt[30:2]==2) struct_dsc <= '{e0:1, e1:2, e2:3, e3:4};
|
||||
else if (cnt[30:2]==3) struct_dsc <= '{e3:6, e2:4, e1:2, e0:0};
|
||||
// verilator lint_off WIDTH
|
||||
else if (cnt[30:2]==4) struct_bg <= '{default:13};
|
||||
else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1};
|
||||
else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
|
||||
else if (cnt[30:2]==4) struct_dsc <= '{default:13};
|
||||
else if (cnt[30:2]==5) struct_dsc <= '{e2:8'haa, default:1};
|
||||
else if (cnt[30:2]==6) struct_dsc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
|
||||
// verilator lint_on WIDTH
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// chack array agains expected value
|
||||
if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (struct_dsc !== 15'b0_00_0000_00000000) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b0_01_0010_00000011) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b1_10_0011_00000100) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b0_10_0100_00000110) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b1_01_1101_00001101) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b1_01_1010_00000001) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (struct_dsc !== 15'b1_10_1011_00011100) begin $display("%b", struct_dsc); $stop(); end end
|
||||
end
|
||||
|
||||
// little endian
|
||||
// ascending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaults (all bits 1'b0)
|
||||
if (cnt[30:2]==0) struct_lt <= '0;
|
||||
else if (cnt[30:2]==1) struct_lt <= '0;
|
||||
else if (cnt[30:2]==2) struct_lt <= '0;
|
||||
else if (cnt[30:2]==3) struct_lt <= '0;
|
||||
else if (cnt[30:2]==4) struct_lt <= '0;
|
||||
else if (cnt[30:2]==5) struct_lt <= '0;
|
||||
else if (cnt[30:2]==6) struct_lt <= '0;
|
||||
if (cnt[30:2]==0) struct_asc <= '0;
|
||||
else if (cnt[30:2]==1) struct_asc <= '0;
|
||||
else if (cnt[30:2]==2) struct_asc <= '0;
|
||||
else if (cnt[30:2]==3) struct_asc <= '0;
|
||||
else if (cnt[30:2]==4) struct_asc <= '0;
|
||||
else if (cnt[30:2]==5) struct_asc <= '0;
|
||||
else if (cnt[30:2]==6) struct_asc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write data into whole or part of the array using literals
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3};
|
||||
else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4};
|
||||
else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0};
|
||||
else if (cnt[30:2]==1) struct_asc <= '{0 ,1 , 2, 3};
|
||||
else if (cnt[30:2]==2) struct_asc <= '{e0:1, e1:2, e2:3, e3:4};
|
||||
else if (cnt[30:2]==3) struct_asc <= '{e3:6, e2:4, e1:2, e0:0};
|
||||
// verilator lint_off WIDTH
|
||||
else if (cnt[30:2]==4) struct_lt <= '{default:13};
|
||||
else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1};
|
||||
else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
|
||||
else if (cnt[30:2]==4) struct_asc <= '{default:13};
|
||||
else if (cnt[30:2]==5) struct_asc <= '{e2:8'haa, default:1};
|
||||
else if (cnt[30:2]==6) struct_asc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
|
||||
// verilator lint_on WIDTH
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// chack array agains expected value
|
||||
if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (struct_asc !== 15'b0_00_0000_00000000) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_asc !== 15'b0_01_0010_00000011) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_asc !== 15'b1_10_0011_00000100) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_asc !== 15'b0_10_0100_00000110) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_asc !== 15'b1_01_1101_00001101) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_asc !== 15'b1_01_1010_00000001) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==6) begin if (struct_asc !== 15'b1_10_1011_00011100) begin $display("%b", struct_asc); $stop(); end end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -19,17 +19,17 @@ module t (/*AUTOARG*/
|
||||
logic [1:0] e1;
|
||||
logic [3:0] e2;
|
||||
logic [7:0] e3;
|
||||
} struct_bg; // big endian structure
|
||||
/* verilator lint_off LITENDIAN */
|
||||
} struct_dsc; // descending range structure
|
||||
/* verilator lint_off ASCRANGE */
|
||||
struct packed {
|
||||
logic e0;
|
||||
logic [0:1] e1;
|
||||
logic [0:3] e2;
|
||||
logic [0:7] e3;
|
||||
} struct_lt; // little endian structure
|
||||
/* verilator lint_on LITENDIAN */
|
||||
} struct_asc; // ascending range structure
|
||||
/* verilator lint_on ASCRANGE */
|
||||
|
||||
localparam WS = 15; // $bits(struct_bg)
|
||||
localparam WS = 15; // $bits(struct_dsc)
|
||||
|
||||
integer cnt = 0;
|
||||
|
||||
@ -46,76 +46,76 @@ module t (/*AUTOARG*/
|
||||
$finish;
|
||||
end
|
||||
|
||||
// big endian
|
||||
// descending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaaults (all bits to 0)
|
||||
if (cnt[30:2]==0) struct_bg <= '0;
|
||||
else if (cnt[30:2]==1) struct_bg <= '0;
|
||||
else if (cnt[30:2]==2) struct_bg <= '0;
|
||||
else if (cnt[30:2]==3) struct_bg <= '0;
|
||||
else if (cnt[30:2]==4) struct_bg <= '0;
|
||||
else if (cnt[30:2]==5) struct_bg <= '0;
|
||||
if (cnt[30:2]==0) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==1) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==2) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==3) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==4) struct_dsc <= '0;
|
||||
else if (cnt[30:2]==5) struct_dsc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write value to structure
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) struct_bg <= '1;
|
||||
else if (cnt[30:2]==2) struct_bg.e0 <= '1;
|
||||
else if (cnt[30:2]==3) struct_bg.e1 <= '1;
|
||||
else if (cnt[30:2]==4) struct_bg.e2 <= '1;
|
||||
else if (cnt[30:2]==5) struct_bg.e3 <= '1;
|
||||
else if (cnt[30:2]==1) struct_dsc <= '1;
|
||||
else if (cnt[30:2]==2) struct_dsc.e0 <= '1;
|
||||
else if (cnt[30:2]==3) struct_dsc.e1 <= '1;
|
||||
else if (cnt[30:2]==4) struct_dsc.e2 <= '1;
|
||||
else if (cnt[30:2]==5) struct_dsc.e3 <= '1;
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// check structure value
|
||||
if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (struct_dsc !== 15'b000000000000000) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b111111111111111) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b100000000000000) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b011000000000000) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b000111100000000) begin $display("%b", struct_dsc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b000000011111111) begin $display("%b", struct_dsc); $stop(); end end
|
||||
end else if (cnt[1:0]==2'd3) begin
|
||||
// read value from structure (not a very good test for now)
|
||||
if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end
|
||||
if (cnt[30:2]==0) begin if (struct_dsc !== {WS{1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (struct_dsc !== {WS{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (struct_dsc.e0 !== { 1{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (struct_dsc.e1 !== { 2{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (struct_dsc.e2 !== { 4{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (struct_dsc.e3 !== { 8{1'b1}}) $stop(); end
|
||||
end
|
||||
|
||||
// little endian
|
||||
// ascending range
|
||||
always @ (posedge clk)
|
||||
if (cnt[1:0]==2'd0) begin
|
||||
// initialize to defaaults (all bits to 0)
|
||||
if (cnt[30:2]==0) struct_lt <= '0;
|
||||
else if (cnt[30:2]==1) struct_lt <= '0;
|
||||
else if (cnt[30:2]==2) struct_lt <= '0;
|
||||
else if (cnt[30:2]==3) struct_lt <= '0;
|
||||
else if (cnt[30:2]==4) struct_lt <= '0;
|
||||
else if (cnt[30:2]==5) struct_lt <= '0;
|
||||
if (cnt[30:2]==0) struct_asc <= '0;
|
||||
else if (cnt[30:2]==1) struct_asc <= '0;
|
||||
else if (cnt[30:2]==2) struct_asc <= '0;
|
||||
else if (cnt[30:2]==3) struct_asc <= '0;
|
||||
else if (cnt[30:2]==4) struct_asc <= '0;
|
||||
else if (cnt[30:2]==5) struct_asc <= '0;
|
||||
end else if (cnt[1:0]==2'd1) begin
|
||||
// write value to structure
|
||||
if (cnt[30:2]==0) begin end
|
||||
else if (cnt[30:2]==1) struct_lt <= '1;
|
||||
else if (cnt[30:2]==2) struct_lt.e0 <= '1;
|
||||
else if (cnt[30:2]==3) struct_lt.e1 <= '1;
|
||||
else if (cnt[30:2]==4) struct_lt.e2 <= '1;
|
||||
else if (cnt[30:2]==5) struct_lt.e3 <= '1;
|
||||
else if (cnt[30:2]==1) struct_asc <= '1;
|
||||
else if (cnt[30:2]==2) struct_asc.e0 <= '1;
|
||||
else if (cnt[30:2]==3) struct_asc.e1 <= '1;
|
||||
else if (cnt[30:2]==4) struct_asc.e2 <= '1;
|
||||
else if (cnt[30:2]==5) struct_asc.e3 <= '1;
|
||||
end else if (cnt[1:0]==2'd2) begin
|
||||
// check structure value
|
||||
if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end
|
||||
if (cnt[30:2]==0) begin if (struct_asc !== 15'b000000000000000) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==1) begin if (struct_asc !== 15'b111111111111111) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==2) begin if (struct_asc !== 15'b100000000000000) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==3) begin if (struct_asc !== 15'b011000000000000) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==4) begin if (struct_asc !== 15'b000111100000000) begin $display("%b", struct_asc); $stop(); end end
|
||||
else if (cnt[30:2]==5) begin if (struct_asc !== 15'b000000011111111) begin $display("%b", struct_asc); $stop(); end end
|
||||
end else if (cnt[1:0]==2'd3) begin
|
||||
// read value from structure (not a very good test for now)
|
||||
if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end
|
||||
if (cnt[30:2]==0) begin if (struct_asc !== {WS{1'b0}}) $stop(); end
|
||||
else if (cnt[30:2]==1) begin if (struct_asc !== {WS{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==2) begin if (struct_asc.e0 !== { 1{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==3) begin if (struct_asc.e1 !== { 2{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==4) begin if (struct_asc.e2 !== { 4{1'b1}}) $stop(); end
|
||||
else if (cnt[30:2]==5) begin if (struct_asc.e3 !== { 8{1'b1}}) $stop(); end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
|
||||
module t;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [5:0] binary_string [2:15];
|
||||
reg [5:0] binary_nostart [2:15];
|
||||
reg [5:0] binary_start [0:15];
|
||||
@ -30,7 +30,7 @@ module t;
|
||||
reg [(32*6)-1:0] hex_align_tmp [0:15];
|
||||
string fns_tmp;
|
||||
`endif
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
integer i;
|
||||
|
||||
|
||||
@ -14,7 +14,7 @@ scenarios(simulator => 1);
|
||||
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
|
||||
# Strangely, asking for more threads makes it go away.
|
||||
compile(
|
||||
verilator_flags2 => ['--cc --trace --trace-params -Wno-LITENDIAN'],
|
||||
verilator_flags2 => ['--cc --trace --trace-params -Wno-ASCRANGE'],
|
||||
threads => $Self->{vltmt} ? 6 : 1
|
||||
);
|
||||
|
||||
@ -10,13 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
top_filename("t/t_trace_litendian.v");
|
||||
top_filename("t/t_trace_ascendingrange.v");
|
||||
|
||||
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
|
||||
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
|
||||
# Strangely, asking for more threads makes it go away.
|
||||
compile(
|
||||
verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-LITENDIAN'],
|
||||
verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-ASCRANGE'],
|
||||
threads => $Self->{vltmt} ? 6 : 1
|
||||
);
|
||||
|
||||
@ -14,13 +14,13 @@ if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_litendian.v");
|
||||
top_filename("t/t_trace_ascendingrange.v");
|
||||
|
||||
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
|
||||
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
|
||||
# Strangely, asking for more threads makes it go away.
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-LITENDIAN'],
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-ASCRANGE'],
|
||||
threads => $Self->{vltmt} ? 6 : 1
|
||||
);
|
||||
|
||||
@ -68,11 +68,11 @@ module little (
|
||||
input clk
|
||||
);
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [0:7] i8; initial i8 = '0;
|
||||
reg [1:49] i48; initial i48 = '0;
|
||||
reg [63:190] i128; initial i128 = '0;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
always @ (posedge clk) begin
|
||||
i8 <= ~i8;
|
||||
|
||||
@ -8,9 +8,9 @@ typedef logic logic_alias_t;
|
||||
|
||||
module t;
|
||||
logic_alias_t [6:1] signal;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
logic_alias_t [1:6] signal2;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
initial begin
|
||||
signal[6:1] = 'b100001;
|
||||
|
||||
@ -30,9 +30,9 @@ extern "C" int mon_check();
|
||||
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/;
|
||||
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
reg [31:0] count /*verilator public_flat_rd */;
|
||||
reg [31:0] half_count /*verilator public_flat_rd */;
|
||||
|
||||
@ -39,11 +39,11 @@ extern "C" int mon_check();
|
||||
reg [2:1] twoone;
|
||||
reg [2:1] fourthreetwoone[4:3];
|
||||
reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
|
||||
// verilator lint_off LITENDIAN
|
||||
// verilator lint_off ASCRANGE
|
||||
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/;
|
||||
/*verilator public_off*/
|
||||
reg invisible1;
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on ASCRANGE
|
||||
|
||||
/*verilator public_flat_rd_on*/
|
||||
reg [31:0] count;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user