diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 622d21859..743f641a4 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -6299,8 +6299,18 @@ private:
         const bool fromNumericable = VN_IS(fromBaseDtp, BasicDType)
                                      || VN_IS(fromBaseDtp, EnumDType)
                                      || VN_IS(fromBaseDtp, NodeUOrStructDType);
+
+        const AstNodeDType* toBaseDtp = toDtp;
+        while (const AstPackArrayDType* const packp = VN_CAST(toBaseDtp, PackArrayDType)) {
+            toBaseDtp = packp->subDTypep();
+            while (const AstRefDType* const refp = VN_CAST(toBaseDtp, RefDType)) {
+                toBaseDtp = refp->refDTypep();
+            }
+        }
+        const bool toNumericable
+            = VN_IS(toBaseDtp, BasicDType) || VN_IS(toBaseDtp, NodeUOrStructDType);
         // UNSUP unpacked struct/unions (treated like BasicDType)
-        if (VN_IS(toDtp, BasicDType) || VN_IS(toDtp, NodeUOrStructDType)) {
+        if (toNumericable) {
             if (fromNumericable) return COMPATIBLE;
         } else if (VN_IS(toDtp, EnumDType)) {
             if (VN_IS(fromBaseDtp, EnumDType) && toDtp->sameTree(fromDtp)) return ENUM_IMPLICIT;
diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v
index bf7ca06c5..6a3990561 100644
--- a/test_regress/t/t_cast.v
+++ b/test_regress/t/t_cast.v
@@ -15,6 +15,7 @@ module t;
 
    typedef logic [3:0] mc_t;
    typedef mc_t tocast_t;
+   typedef logic [2:0] [7:0] two_dee_t;
 
    typedef struct packed {
       logic [15:0] data;
@@ -42,6 +43,8 @@ module t;
    logic [15:0] allones = 16'hffff;
    parameter FOUR = 4;
 
+   localparam two_dee_t two_dee = two_dee_t'(32'habcdef);
+
    // bug925
    localparam [6:0] RESULT = 7'((6*9+92)%96);
 
@@ -63,6 +66,9 @@ module t;
    logic [32:0] b33 = {32'(0), one};
    logic [31:0] b32 = {31'(0), one};
 
+   logic [31:0] thirty_two_bits;
+   two_dee_t two_dee_sig;
+
    initial begin
       if (logic8bit != 8'h12) $stop;
       if (4'shf > 4'sh0) $stop;
@@ -107,6 +113,17 @@ module t;
       if (b33 != 33'b1) $stop;
       if (b32 != 32'b1) $stop;
 
+      if (two_dee[0] != 8'hef) $stop;
+      if (two_dee[1] != 8'hcd) $stop;
+      if (two_dee[2] != 8'hab) $stop;
+
+      thirty_two_bits = 32'h123456;
+      two_dee_sig = two_dee_t'(thirty_two_bits);
+
+      if (two_dee_sig[0] != 8'h56) $stop;
+      if (two_dee_sig[1] != 8'h34) $stop;
+      if (two_dee_sig[2] != 8'h12) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end