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Fix undeclared VL_SHIFTR_WWQ, #2114.

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Wilson Snyder 2020-02-23 19:33:37 -05:00
parent 18f8cd0529
commit 28e19cef90
3 changed files with 98 additions and 80 deletions
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8
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@ -5,8 +5,12 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 4.029 devel
*** Add assertOn check for assert. [Tobias Wölfel]
*** Add +verilator+noassert flag to disable assert checking. [Tobias Wölfel]
*** Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel]
*** Add check for assertOn for asserts, #2162. [Tobias Wölfel]
**** Fix undeclared VL_SHIFTR_WWQ, #2114. [Alex Solomatnikov]
* Verilator 4.028 2020-02-08

11
include/verilated.h
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@ -2013,6 +2013,12 @@ static inline WDataOutP VL_SHIFTR_WWW(int obits, int lbits, int rbits,
}
return VL_SHIFTR_WWI(obits, lbits, 32, owp, lwp, rwp[0]);
}
static inline WDataOutP VL_SHIFTR_WWQ(int obits, int lbits, int rbits,
WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE {
WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd);
return VL_SHIFTR_WWW(obits, lbits, rbits, owp, lwp, rwp);
}
static inline IData VL_SHIFTR_IIW(int obits, int, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE {
for (int i = 1; i < VL_WORDS_I(rbits); ++i) {
if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
@ -2098,6 +2104,11 @@ static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits,
}
return VL_SHIFTRS_WWI(obits, lbits, 32, owp, lwp, rwp[0]);
}
static inline WDataOutP VL_SHIFTRS_WWQ(int obits, int lbits, int rbits,
WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE {
WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd);
return VL_SHIFTRS_WWW(obits, lbits, rbits, owp, lwp, rwp);
}
static inline IData VL_SHIFTRS_IIW(int obits, int lbits, int rbits,
IData lhs, WDataInP rwp) VL_MT_SAFE {
EData overshift = 0; // Huge shift 1>>32 or more

5
test_regress/t/t_math_shift.v
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@ -5,7 +5,7 @@
module t (/*AUTOARG*/
// Outputs
ign, ign2, ign3,
ign, ign2, ign3, ign4, ign4s,
// Inputs
clk
);
@ -38,6 +38,9 @@ module t (/*AUTOARG*/
amt[1:0] << {22{amt[5:2]}},
amt[1:0] << {11{amt[5:2]}}};
wire [95:0] wamt = {amt,amt,amt};
output wire [95:0] ign4 = wamt >> {11{amt[5:2]}};
output wire signed [95:0] ign4s = $signed(wamt) >>> {11{amt[5:2]}};
always @* begin
right = 32'h819b018a >> amt;