diff --git a/Changes b/Changes index a9e55a251..622946f16 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix task inlining under $display, bug589. [Holger Waechtler] +**** Fix package import of non-localparam parameter, bug591. [Jeremy Bennett] + * Verilator 3.843 2012/12/01 diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index ab898c6af..eeb5ee3a0 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -247,7 +247,7 @@ public: abovep->reinsert(name, symp); return symp; } - void insertSym(VSymEnt* abovep, const string& name, AstNode* nodep, AstPackage* packagep) { + VSymEnt* insertSym(VSymEnt* abovep, const string& name, AstNode* nodep, AstPackage* packagep) { if (!abovep) nodep->v3fatalSrc("Null symbol table inserting node"); VSymEnt* symp = new VSymEnt(&m_syms, nodep); UINFO(9," INSERTsym se"<<(void*)symp<<" name='"<insertSym(m_curSymp, "__paramNumber"+cvtToStr(m_paramNum), nodep, m_packagep); + symp->importable(false); } } } @@ -752,6 +754,7 @@ private: } } m_curSymp->import(srcp, nodep->name()); + UINFO(2," Link Done: "<v3error("Pin is not an in/out/inout: "<prettyName()); } else { refp->user4(true); - m_statep->insertSym(m_statep->getNodeSym(m_modp), "__pinNumber"+cvtToStr(nodep->pinNum()), refp, NULL/*packagep*/); + VSymEnt* symp = m_statep->insertSym(m_statep->getNodeSym(m_modp), + "__pinNumber"+cvtToStr(nodep->pinNum()), refp, NULL/*packagep*/); + symp->importable(false); } // Ports not needed any more nodep->unlinkFrBack()->deleteTree(); nodep=NULL; diff --git a/src/V3SymTable.h b/src/V3SymTable.h index cddd0a32f..de3790b74 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -53,6 +53,7 @@ private: VSymEnt* m_parentp; // Table that created this table, dot notation needed to resolve into it AstPackage* m_packagep; // Package node is in (for V3LinkDot, unused here) string m_symPrefix; // String to prefix symbols with (for V3LinkDot, unused here) + bool m_importable; // Allow importing #ifdef VL_DEBUG static int debug() { static int level = -1; @@ -107,6 +108,8 @@ public: AstNode* nodep() const { if (!this) return NULL; else return m_nodep; } // null check so can call .findId(...)->nodep() string symPrefix() const { return m_symPrefix; } void symPrefix(const string& name) { m_symPrefix = name; } + bool importable() const { return m_importable; } + void importable(bool flag) { m_importable = flag; } void insert(const string& name, VSymEnt* entp) { UINFO(9, " SymInsert se"<<(void*)this<<" '"<nodep()<m_idNameMap.find(id_or_star); if (it != m_idNameMap.end()) { - reinsert(it->first, it->second); - any = true; + if (it->second->importable()) { + reinsert(it->first, it->second); + } } + any = true; // Legal, though perhaps lint questionable to import nothing } else { for (IdNameMap::const_iterator it=srcp->m_idNameMap.begin(); it!=srcp->m_idNameMap.end(); ++it) { - reinsert(it->first, it->second); - any = true; + if (it->second->importable()) { + reinsert(it->first, it->second); + any = true; + } } } return any; @@ -244,6 +251,7 @@ inline VSymEnt::VSymEnt(VSymGraph* m_graphp, AstNode* nodep) m_fallbackp = NULL; m_parentp = NULL; m_packagep = NULL; + m_importable = true; m_graphp->pushNewEnt(this); } diff --git a/test_regress/t/t_package_twodeep.pl b/test_regress/t/t_package_twodeep.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_package_twodeep.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v new file mode 100644 index 000000000..c8c8ed4a3 --- /dev/null +++ b/test_regress/t/t_package_twodeep.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett + +// see bug 591 + +package pkg2; + parameter PARAM2 = 16; +endpackage // pkg2 + +package pkg1; + import pkg2::*; + parameter PARAM1 = 8; +endpackage // pkg1 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + import pkg1::*; + + reg [PARAM1:0] bus1; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule