From 27232238848d836e6d92815767c875ca8de83084 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 18 Oct 2022 17:29:51 -0400 Subject: [PATCH] Fix LSB error on --hierarchical submodules (#3539). --- Changes | 1 + src/V3EmitV.cpp | 4 +- test_regress/t/t_hier_block.v | 4 +- test_regress/t/t_hier_block_sc_trace_fst.out | 8 +- test_regress/t/t_hier_block_sc_trace_vcd.out | 220 +++++++++---------- test_regress/t/t_hier_block_trace_fst.out | 8 +- test_regress/t/t_hier_block_trace_vcd.out | 192 ++++++++-------- 7 files changed, 220 insertions(+), 217 deletions(-) diff --git a/Changes b/Changes index 1d06c5041..f4ca620a8 100644 --- a/Changes +++ b/Changes @@ -38,6 +38,7 @@ Verilator 5.001 devel * Add error on real edge event control. * Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd] * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd] +* Fix LSB error on --hierarchical submodules (#3539). [danbone] Verilator 4.228 2022-10-01 diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index ce76d6135..3b2d6a3fd 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -597,7 +597,9 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } else if (nodep->isRanged()) { puts(" ["); puts(cvtToStr(nodep->hi())); - puts(":0] "); + puts(":"); + puts(cvtToStr(nodep->lo())); + puts("] "); } } void visit(AstConstDType* nodep) override { diff --git a/test_regress/t/t_hier_block.v b/test_regress/t/t_hier_block.v index 6e1d37098..e7c67c615 100644 --- a/test_regress/t/t_hier_block.v +++ b/test_regress/t/t_hier_block.v @@ -115,7 +115,7 @@ endmodule module sub1( input wire clk, - input wire [7:0] in, + input wire [11:4] in, // Uses higher LSB to cover bug3539 output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; @@ -131,7 +131,7 @@ module sub2( logic [7:0] ff; - // dpi_import_func returns (dpi_eport_func(v) -1) + // dpi_import_func returns (dpi_eport_func(v) -1) import "DPI-C" context function int dpi_import_func(int v); export "DPI-C" function dpi_export_func; diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_hier_block_sc_trace_fst.out index 0594e8107..325da4741 100644 --- a/test_regress/t/t_hier_block_sc_trace_fst.out +++ b/test_regress/t/t_hier_block_sc_trace_fst.out @@ -1,5 +1,5 @@ $date - Tue Feb 22 23:52:17 2022 + Tue Oct 18 17:13:03 2022 $end $version @@ -41,7 +41,7 @@ $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 ! clk $end -$var wire 8 " in [7:0] $end +$var wire 8 " in [11:4] $end $var wire 8 # out [7:0] $end $upscope $end $scope module i_sub2 $end @@ -128,11 +128,11 @@ $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 > clk $end -$var wire 8 ? in [7:0] $end +$var wire 8 ? in [11:4] $end $var wire 8 @ out [7:0] $end $scope module sub1 $end $var wire 1 > clk $end -$var wire 8 ? in [7:0] $end +$var wire 8 ? in [11:4] $end $var wire 8 @ out [7:0] $end $var logic 8 A ff [7:0] $end $upscope $end diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_hier_block_sc_trace_vcd.out index 6e0c6affa..cde885b1e 100644 --- a/test_regress/t/t_hier_block_sc_trace_vcd.out +++ b/test_regress/t/t_hier_block_sc_trace_vcd.out @@ -1,57 +1,57 @@ $version Generated by VerilatedVcd $end -$date Sun Dec 19 12:27:52 2021 $end +$date Tue Oct 18 17:12:31 2022 $end $timescale 1ps $end $scope module top $end $scope module t $end - $var wire 1 # clk $end + $var wire 1 * clk $end $var wire 32 + count [31:0] $end - $var wire 8 $ out0 [7:0] $end - $var wire 8 % out1 [7:0] $end - $var wire 8 & out2 [7:0] $end - $var wire 8 ' out3 [7:0] $end - $var wire 8 * out3_2 [7:0] $end + $var wire 8 # out0 [7:0] $end + $var wire 8 $ out1 [7:0] $end + $var wire 8 % out2 [7:0] $end + $var wire 8 & out3 [7:0] $end + $var wire 8 ' out3_2 [7:0] $end $var wire 8 ( out5 [7:0] $end $var wire 8 ) out6 [7:0] $end $scope module i_delay0 $end - $var wire 1 # clk $end - $var wire 8 ' in [7:0] $end + $var wire 1 * clk $end + $var wire 8 & in [7:0] $end $var wire 8 ( out [7:0] $end $upscope $end $scope module i_delay1 $end - $var wire 1 # clk $end + $var wire 1 * clk $end $var wire 8 ( in [7:0] $end $var wire 8 ) out [7:0] $end $upscope $end $scope module i_sub0 $end - $var wire 1 # clk $end - $var wire 8 ' in [7:0] $end - $var wire 8 $ out [7:0] $end + $var wire 1 * clk $end + $var wire 8 & in [7:0] $end + $var wire 8 # out [7:0] $end $scope module i_sub0 $end - $var wire 1 # clk $end - $var wire 8 ' in [7:0] $end - $var wire 8 $ out [7:0] $end + $var wire 1 * clk $end + $var wire 8 & in [7:0] $end + $var wire 8 # out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end - $var wire 1 # clk $end + $var wire 1 * clk $end + $var wire 8 # in [11:4] $end + $var wire 8 $ out [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 1 * clk $end $var wire 8 $ in [7:0] $end $var wire 8 % out [7:0] $end $upscope $end - $scope module i_sub2 $end - $var wire 1 # clk $end + $scope module i_sub3 $end + $var wire 1 * clk $end $var wire 8 % in [7:0] $end $var wire 8 & out [7:0] $end $upscope $end - $scope module i_sub3 $end - $var wire 1 # clk $end - $var wire 8 & in [7:0] $end - $var wire 8 ' out [7:0] $end - $upscope $end $scope module i_sub3_2 $end - $var wire 1 # clk $end - $var wire 8 & in [7:0] $end - $var wire 8 * out [7:0] $end + $var wire 1 * clk $end + $var wire 8 % in [7:0] $end + $var wire 8 ' out [7:0] $end $upscope $end $upscope $end $upscope $end @@ -122,12 +122,12 @@ $timescale 1ps $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 D clk $end - $var wire 8 E in [7:0] $end + $var wire 8 E in [11:4] $end $var wire 8 F out [7:0] $end $scope module sub1 $end $var wire 1 D clk $end $var wire 8 G ff [7:0] $end - $var wire 8 E in [7:0] $end + $var wire 8 E in [11:4] $end $var wire 8 F out [7:0] $end $upscope $end $upscope $end @@ -1016,14 +1016,14 @@ $enddefinitions $end #0 -0# +b00000000 # b00000000 $ b00000000 % b00000000 & b00000000 ' b00000000 ( b00000000 ) -b00000000 * +0* b00000000000000000000000000000000 + 0- b00000000 . @@ -1502,11 +1502,11 @@ b00000001 ') b00000011 () b00000000000000000000000000000001 )) #10 -1# -b00000001 % +b00000001 $ +b00000010 % b00000010 & b00000010 ' -b00000010 * +1* b00000000000000000000000000000001 + 1- b00000010 . @@ -1677,7 +1677,7 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000 #13 #14 #15 -0# +0* 0- 08 0? @@ -1703,11 +1703,11 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000 #18 #19 #20 -1# -b00000010 $ -b00000101 & +b00000010 # +b00000101 % +b00000011 & b00000011 ' -b00000011 * +1* b00000000000000000000000000000010 + 1- b00000011 . @@ -2017,7 +2017,7 @@ b00000001 #) #23 #24 #25 -0# +0* 0- 08 0? @@ -2043,13 +2043,13 @@ b00000001 #) #28 #29 #30 -1# +b00000011 # b00000011 $ -b00000011 % -b00000111 & +b00000111 % +b00000101 & b00000101 ' b00000010 ( -b00000101 * +1* b00000000000000000000000000000011 + 1- b00000101 . @@ -2345,7 +2345,7 @@ b00000000 #) #33 #34 #35 -0# +0* 0- 08 0? @@ -2371,13 +2371,13 @@ b00000000 #) #38 #39 #40 -1# -b00000101 $ -b00000100 % +b00000101 # +b00000100 $ +b00001000 % b00001000 & b00001000 ' b00000011 ( -b00001000 * +1* b00000000000000000000000000000100 + 1- b00001000 . @@ -2673,7 +2673,7 @@ b00000001 #) #43 #44 #45 -0# +0* 0- 08 0? @@ -2699,12 +2699,12 @@ b00000001 #) #48 #49 #50 -1# -b00001000 $ -b00000110 % +b00001000 # +b00000110 $ +b00001010 & b00001010 ' b00000101 ( -b00001010 * +1* b00000000000000000000000000000101 + 1- b00001010 . @@ -2992,7 +2992,7 @@ b00000000 #) #53 #54 #55 -0# +0* 0- 08 0? @@ -3018,14 +3018,14 @@ b00000000 #) #58 #59 #60 -1# -b00001010 $ -b00001001 % -b00001010 & +b00001010 # +b00001001 $ +b00001010 % +b00001011 & b00001011 ' b00001000 ( b00000010 ) -b00001011 * +1* b00000000000000000000000000000110 + 1- b00001011 . @@ -3321,7 +3321,7 @@ b00000001 #) #63 #64 #65 -0# +0* 0- 08 0? @@ -3347,12 +3347,12 @@ b00000001 #) #68 #69 #70 -1# +b00001011 # b00001011 $ b00001011 % -b00001011 & b00001010 ( b00000011 ) +1* b00000000000000000000000000000111 + 1- b00001010 / @@ -3638,7 +3638,7 @@ b00000000 #) #73 #74 #75 -0# +0* 0- 08 0? @@ -3664,13 +3664,13 @@ b00000000 #) #78 #79 #80 -1# -b00001100 % +b00001100 $ +b00001101 % b00001101 & b00001101 ' b00001011 ( b00000101 ) -b00001101 * +1* b00000000000000000000000000001000 + 1- b00001101 . @@ -3968,7 +3968,7 @@ b00000001 #) #83 #84 #85 -0# +0* 0- 08 0? @@ -3994,12 +3994,12 @@ b00000001 #) #88 #89 #90 -1# -b00001101 $ -b00010000 & +b00001101 # +b00010000 % +b00001110 & b00001110 ' b00001000 ) -b00001110 * +1* b00000000000000000000000000001001 + 1- b00001110 . @@ -4295,7 +4295,7 @@ b00000000 #) #93 #94 #95 -0# +0* 0- 08 0? @@ -4321,14 +4321,14 @@ b00000000 #) #98 #99 #100 -1# +b00001110 # b00001110 $ -b00001110 % -b00010010 & +b00010010 % +b00010000 & b00010000 ' b00001101 ( b00001010 ) -b00010000 * +1* b00000000000000000000000000001010 + 1- b00010000 . @@ -4627,7 +4627,7 @@ b00000001 #) #103 #104 #105 -0# +0* 0- 08 0? @@ -4653,14 +4653,14 @@ b00000001 #) #108 #109 #110 -1# -b00010000 $ -b00001111 % +b00010000 # +b00001111 $ +b00010011 % b00010011 & b00010011 ' b00001110 ( b00001011 ) -b00010011 * +1* b00000000000000000000000000001011 + 1- b00010011 . @@ -4958,7 +4958,7 @@ b00000000 #) #113 #114 #115 -0# +0* 0- 08 0? @@ -4984,12 +4984,12 @@ b00000000 #) #118 #119 #120 -1# -b00010011 $ -b00010001 % +b00010011 # +b00010001 $ +b00010101 & b00010101 ' b00010000 ( -b00010101 * +1* b00000000000000000000000000001100 + 1- b00010101 . @@ -5277,7 +5277,7 @@ b00000001 #) #123 #124 #125 -0# +0* 0- 08 0? @@ -5303,14 +5303,14 @@ b00000001 #) #128 #129 #130 -1# -b00010101 $ -b00010100 % -b00010101 & +b00010101 # +b00010100 $ +b00010101 % +b00010110 & b00010110 ' b00010011 ( b00001101 ) -b00010110 * +1* b00000000000000000000000000001101 + 1- b00010110 . @@ -5606,7 +5606,7 @@ b00000000 #) #133 #134 #135 -0# +0* 0- 08 0? @@ -5632,12 +5632,12 @@ b00000000 #) #138 #139 #140 -1# +b00010110 # b00010110 $ b00010110 % -b00010110 & b00010101 ( b00001110 ) +1* b00000000000000000000000000001110 + 1- b00010101 / @@ -5923,7 +5923,7 @@ b00000001 #) #143 #144 #145 -0# +0* 0- 08 0? @@ -5949,13 +5949,13 @@ b00000001 #) #148 #149 #150 -1# -b00010111 % +b00010111 $ +b00011000 % b00011000 & b00011000 ' b00010110 ( b00010000 ) -b00011000 * +1* b00000000000000000000000000001111 + 1- b00011000 . @@ -6253,7 +6253,7 @@ b00000000 #) #153 #154 #155 -0# +0* 0- 08 0? @@ -6279,12 +6279,12 @@ b00000000 #) #158 #159 #160 -1# -b00011000 $ -b00011011 & +b00011000 # +b00011011 % +b00011001 & b00011001 ' b00010011 ) -b00011001 * +1* b00000000000000000000000000010000 + 1- b00011001 . @@ -6580,7 +6580,7 @@ b00000001 #) #163 #164 #165 -0# +0* 0- 08 0? @@ -6606,14 +6606,14 @@ b00000001 #) #168 #169 #170 -1# +b00011001 # b00011001 $ -b00011001 % -b00011101 & +b00011101 % +b00011011 & b00011011 ' b00011000 ( b00010101 ) -b00011011 * +1* b00000000000000000000000000010001 + 1- b00011011 . diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_hier_block_trace_fst.out index 366eef0b4..1ae808652 100644 --- a/test_regress/t/t_hier_block_trace_fst.out +++ b/test_regress/t/t_hier_block_trace_fst.out @@ -1,5 +1,5 @@ $date - Tue Feb 22 23:53:34 2022 + Tue Oct 18 17:19:55 2022 $end $version @@ -42,7 +42,7 @@ $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 ! clk $end -$var wire 8 " in [7:0] $end +$var wire 8 " in [11:4] $end $var wire 8 # out [7:0] $end $upscope $end $scope module i_sub2 $end @@ -129,11 +129,11 @@ $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 > clk $end -$var wire 8 ? in [7:0] $end +$var wire 8 ? in [11:4] $end $var wire 8 @ out [7:0] $end $scope module sub1 $end $var wire 1 > clk $end -$var wire 8 ? in [7:0] $end +$var wire 8 ? in [11:4] $end $var wire 8 @ out [7:0] $end $var logic 8 A ff [7:0] $end $upscope $end diff --git a/test_regress/t/t_hier_block_trace_vcd.out b/test_regress/t/t_hier_block_trace_vcd.out index cd600aaa9..993b40bbe 100644 --- a/test_regress/t/t_hier_block_trace_vcd.out +++ b/test_regress/t/t_hier_block_trace_vcd.out @@ -1,58 +1,58 @@ $version Generated by VerilatedVcd $end -$date Sat Nov 27 16:51:43 2021 $end +$date Tue Oct 18 17:20:50 2022 $end $timescale 1ps $end $scope module top $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $scope module t $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 32 + count [31:0] $end $var wire 8 # out0 [7:0] $end $var wire 8 $ out1 [7:0] $end $var wire 8 % out2 [7:0] $end $var wire 8 & out3 [7:0] $end - $var wire 8 * out3_2 [7:0] $end - $var wire 8 ' out5 [7:0] $end - $var wire 8 ( out6 [7:0] $end + $var wire 8 ' out3_2 [7:0] $end + $var wire 8 ( out5 [7:0] $end + $var wire 8 ) out6 [7:0] $end $scope module i_delay0 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 & in [7:0] $end - $var wire 8 ' out [7:0] $end - $upscope $end - $scope module i_delay1 $end - $var wire 1 ) clk $end - $var wire 8 ' in [7:0] $end $var wire 8 ( out [7:0] $end $upscope $end + $scope module i_delay1 $end + $var wire 1 * clk $end + $var wire 8 ( in [7:0] $end + $var wire 8 ) out [7:0] $end + $upscope $end $scope module i_sub0 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 & in [7:0] $end $var wire 8 # out [7:0] $end $scope module i_sub0 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 & in [7:0] $end $var wire 8 # out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end - $var wire 1 ) clk $end - $var wire 8 # in [7:0] $end + $var wire 1 * clk $end + $var wire 8 # in [11:4] $end $var wire 8 $ out [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 $ in [7:0] $end $var wire 8 % out [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 % in [7:0] $end $var wire 8 & out [7:0] $end $upscope $end $scope module i_sub3_2 $end - $var wire 1 ) clk $end + $var wire 1 * clk $end $var wire 8 % in [7:0] $end - $var wire 8 * out [7:0] $end + $var wire 8 ' out [7:0] $end $upscope $end $upscope $end $upscope $end @@ -123,12 +123,12 @@ $timescale 1ps $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 D clk $end - $var wire 8 E in [7:0] $end + $var wire 8 E in [11:4] $end $var wire 8 F out [7:0] $end $scope module sub1 $end $var wire 1 D clk $end $var wire 8 G ff [7:0] $end - $var wire 8 E in [7:0] $end + $var wire 8 E in [11:4] $end $var wire 8 F out [7:0] $end $upscope $end $upscope $end @@ -1023,8 +1023,8 @@ b00000000 % b00000000 & b00000000 ' b00000000 ( -0) -b00000000 * +b00000000 ) +0* b00000000000000000000000000000000 + 0- b00000000 . @@ -1506,8 +1506,8 @@ b00000000000000000000000000000001 )) b00000001 $ b00000010 % b00000010 & -1) -b00000010 * +b00000010 ' +1* b00000000000000000000000000000001 + 1- b00000010 . @@ -1674,7 +1674,7 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x( #15 -0) +0* 0- 08 0? @@ -1699,8 +1699,8 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000 b00000010 # b00000101 % b00000011 & -1) -b00000011 * +b00000011 ' +1* b00000000000000000000000000000010 + 1- b00000011 . @@ -2006,7 +2006,7 @@ b00000011 !) b00000010 ") b00000001 #) #25 -0) +0* 0- 08 0? @@ -2032,9 +2032,9 @@ b00000011 # b00000011 $ b00000111 % b00000101 & -b00000010 ' -1) -b00000101 * +b00000101 ' +b00000010 ( +1* b00000000000000000000000000000011 + 1- b00000101 . @@ -2326,7 +2326,7 @@ b00000000 !) b00000000 ") b00000000 #) #35 -0) +0* 0- 08 0? @@ -2352,9 +2352,9 @@ b00000101 # b00000100 $ b00001000 % b00001000 & -b00000011 ' -1) -b00001000 * +b00001000 ' +b00000011 ( +1* b00000000000000000000000000000100 + 1- b00001000 . @@ -2646,7 +2646,7 @@ b00000011 !) b00000010 ") b00000001 #) #45 -0) +0* 0- 08 0? @@ -2671,9 +2671,9 @@ b00000001 #) b00001000 # b00000110 $ b00001010 & -b00000101 ' -1) -b00001010 * +b00001010 ' +b00000101 ( +1* b00000000000000000000000000000101 + 1- b00001010 . @@ -2957,7 +2957,7 @@ b00000000 !) b00000000 ") b00000000 #) #55 -0) +0* 0- 08 0? @@ -2983,10 +2983,10 @@ b00001010 # b00001001 $ b00001010 % b00001011 & -b00001000 ' -b00000010 ( -1) -b00001011 * +b00001011 ' +b00001000 ( +b00000010 ) +1* b00000000000000000000000000000110 + 1- b00001011 . @@ -3278,7 +3278,7 @@ b00000011 !) b00000010 ") b00000001 #) #65 -0) +0* 0- 08 0? @@ -3303,9 +3303,9 @@ b00000001 #) b00001011 # b00001011 $ b00001011 % -b00001010 ' -b00000011 ( -1) +b00001010 ( +b00000011 ) +1* b00000000000000000000000000000111 + 1- b00001010 / @@ -3587,7 +3587,7 @@ b00000000 !) b00000000 ") b00000000 #) #75 -0) +0* 0- 08 0? @@ -3612,10 +3612,10 @@ b00000000 #) b00001100 $ b00001101 % b00001101 & -b00001011 ' -b00000101 ( -1) -b00001101 * +b00001101 ' +b00001011 ( +b00000101 ) +1* b00000000000000000000000000001000 + 1- b00001101 . @@ -3909,7 +3909,7 @@ b00000011 !) b00000010 ") b00000001 #) #85 -0) +0* 0- 08 0? @@ -3934,9 +3934,9 @@ b00000001 #) b00001101 # b00010000 % b00001110 & -b00001000 ( -1) -b00001110 * +b00001110 ' +b00001000 ) +1* b00000000000000000000000000001001 + 1- b00001110 . @@ -4228,7 +4228,7 @@ b00000000 !) b00000000 ") b00000000 #) #95 -0) +0* 0- 08 0? @@ -4254,10 +4254,10 @@ b00001110 # b00001110 $ b00010010 % b00010000 & -b00001101 ' -b00001010 ( -1) -b00010000 * +b00010000 ' +b00001101 ( +b00001010 ) +1* b00000000000000000000000000001010 + 1- b00010000 . @@ -4552,7 +4552,7 @@ b00000011 !) b00000010 ") b00000001 #) #105 -0) +0* 0- 08 0? @@ -4578,10 +4578,10 @@ b00010000 # b00001111 $ b00010011 % b00010011 & -b00001110 ' -b00001011 ( -1) -b00010011 * +b00010011 ' +b00001110 ( +b00001011 ) +1* b00000000000000000000000000001011 + 1- b00010011 . @@ -4875,7 +4875,7 @@ b00000000 !) b00000000 ") b00000000 #) #115 -0) +0* 0- 08 0? @@ -4900,9 +4900,9 @@ b00000000 #) b00010011 # b00010001 $ b00010101 & -b00010000 ' -1) -b00010101 * +b00010101 ' +b00010000 ( +1* b00000000000000000000000000001100 + 1- b00010101 . @@ -5186,7 +5186,7 @@ b00000011 !) b00000010 ") b00000001 #) #125 -0) +0* 0- 08 0? @@ -5212,10 +5212,10 @@ b00010101 # b00010100 $ b00010101 % b00010110 & -b00010011 ' -b00001101 ( -1) -b00010110 * +b00010110 ' +b00010011 ( +b00001101 ) +1* b00000000000000000000000000001101 + 1- b00010110 . @@ -5507,7 +5507,7 @@ b00000000 !) b00000000 ") b00000000 #) #135 -0) +0* 0- 08 0? @@ -5532,9 +5532,9 @@ b00000000 #) b00010110 # b00010110 $ b00010110 % -b00010101 ' -b00001110 ( -1) +b00010101 ( +b00001110 ) +1* b00000000000000000000000000001110 + 1- b00010101 / @@ -5816,7 +5816,7 @@ b00000011 !) b00000010 ") b00000001 #) #145 -0) +0* 0- 08 0? @@ -5841,10 +5841,10 @@ b00000001 #) b00010111 $ b00011000 % b00011000 & -b00010110 ' -b00010000 ( -1) -b00011000 * +b00011000 ' +b00010110 ( +b00010000 ) +1* b00000000000000000000000000001111 + 1- b00011000 . @@ -6138,7 +6138,7 @@ b00000000 !) b00000000 ") b00000000 #) #155 -0) +0* 0- 08 0? @@ -6163,9 +6163,9 @@ b00000000 #) b00011000 # b00011011 % b00011001 & -b00010011 ( -1) -b00011001 * +b00011001 ' +b00010011 ) +1* b00000000000000000000000000010000 + 1- b00011001 . @@ -6457,7 +6457,7 @@ b00000011 !) b00000010 ") b00000001 #) #165 -0) +0* 0- 08 0? @@ -6483,10 +6483,10 @@ b00011001 # b00011001 $ b00011101 % b00011011 & -b00011000 ' -b00010101 ( -1) -b00011011 * +b00011011 ' +b00011000 ( +b00010101 ) +1* b00000000000000000000000000010001 + 1- b00011011 .