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Fix --timescale-override not suppressing TIMESCALEMOD (#2838).

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This commit is contained in:
Wilson Snyder 2021-03-16 22:42:28 -04:00
parent 12eb4e85ac
commit 26c0fa0a6a
6 changed files with 31 additions and 22 deletions
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1
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@ -19,6 +19,7 @@ Verilator 4.201 devel
* Fix class unpacked-array compile error (#2774). [Iru Cai]
* Fix exceeding command-line ar limit (#2834). [Yinan Xu]
* Fix false $dumpfile warning on model save (#2834). [Yinan Xu]
* Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett]
Verilator 4.200 2021-03-12

8
src/V3LinkLevel.cpp
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@ -102,8 +102,12 @@ void V3LinkLevel::timescaling(const ModVec& mods) {
for (AstNodeModule* nodep : mods) {
if (nodep->timeunit().isNone()) {
if (modTimedp && !VN_IS(nodep, Iface) && !VN_IS(nodep, Primitive)
&& !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit())) {
if (modTimedp // Got previous
&& ( // unit doesn't already include an override
v3Global.opt.timeOverrideUnit().isNone()
&& v3Global.opt.timeDefaultUnit().isNone())
&& (!VN_IS(nodep, Iface) && !VN_IS(nodep, Primitive)
&& !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit()))) {
nodep->v3warn(TIMESCALEMOD,
"Timescale missing on this module as other modules have "
"it (IEEE 1800-2017 3.14.2.3)\n"

20
test_regress/t/t_timescale_lint2.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
top_filename("t/t_timescale_lint.v");
lint(
verilator_flags2 => ["--lint-only --timescale 1ns/1ns"],
);
ok(1);
1;

4
test_regress/t/t_timescale_lint_bad.out
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@ -1,7 +1,7 @@
%Warning-TIMESCALEMOD: t/t_timescale_lint_bad.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3)
%Warning-TIMESCALEMOD: t/t_timescale_lint.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3)
7 | module pre_no_ts;
| ^~~~~~~~~
t/t_timescale_lint_bad.v:12:8: ... Location of module with timescale
t/t_timescale_lint.v:12:8: ... Location of module with timescale
12 | module t;
| ^
... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message.

2
test_regress/t/t_timescale_lint_bad.pl
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@ -10,6 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(linter => 1);
top_filename("t/t_timescale_lint.v");
lint(
verilator_flags2 => ["--lint-only"],
fails => 1,

18
test_regress/t/t_timescale_lint_bad.v
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@ -1,18 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under The Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module pre_no_ts;
endmodule
`timescale 1ns/1ns
module t;
pre_no_ts pre_no_ts();
post_no_ts pst_no_ts();
endmodule
module post_no_ts;
endmodule