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Tests: Move old-style test_v's t_arith, etc to test_regress area

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This commit is contained in:
Wilson Snyder 2010-01-09 21:19:30 -05:00
parent a2629c4929
commit 266b3b8678
15 changed files with 159 additions and 118 deletions
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18
test_regress/t/t_func_first.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

9
test_v/t_task.v → test_regress/t/t_func_first.v
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@ -4,20 +4,16 @@
// without warranty, 2003 by Wilson Snyder.
module t_task (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
reg [7:0] cyc; initial cyc=0;
reg set_in_task;
always @ (posedge clk) begin
if (cyc == 8'd0) begin
$write("[%0t] t_task: Starting\n",$time);
cyc <= 8'd1;
set_in_task <= 0;
end
@ -27,15 +23,14 @@ module t_task (/*AUTOARG*/
end
if (cyc == 8'd2) begin
if (!set_in_task) $stop;
$write("[%0t] t_task: Passed\n",$time);
cyc <= 8'hf;
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end
task ttask;
begin
$write("[%0t] t_task: In task\n",$time);
set_in_task <= 1'b1;
end
endtask

18
test_regress/t/t_func_grey.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

36
test_v/t_func_grey2bin.v → test_regress/t/t_func_grey.v
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@ -1,9 +1,41 @@
// -*- Verilog -*-
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//====================================================================
module t_func (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off _NETNM
// surefire lint_off STMINI
input clk;
integer _mode; initial _mode = 0;
wire [2:0] b3; reg [2:0] g3;
wire [5:0] b6; reg [5:0] g6;
t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
always @ (posedge clk) begin
if (_mode==0) begin
_mode <= 1;
g3 <= 3'b101;
g6 <= 6'b110101;
end
else if (_mode==1) begin
if (b3 !== 3'b110) $stop;
if (b6 !== 6'b100110) $stop;
_mode <= 2;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
// Module gray2bin
// convert an arbitrary width gray coded number to binary. The conversion

18
test_regress/t/t_initial.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

10
test_v/t_initial.v → test_regress/t/t_initial.v
View File

@ -3,14 +3,11 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_initial(/*AUTOARG*/
// Outputs
passed,
module t_initial (/*AUTOARG*/
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
reg _ranit;
`include "t_initial_inc.v"
@ -23,7 +20,6 @@ module t_initial(/*AUTOARG*/
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_initial: Running\n",$time);
// Test $time
// surefire lint_off CWECBB
@ -41,8 +37,8 @@ module t_initial(/*AUTOARG*/
`endif
user_loaded_value <= 2;
$write("[%0t] t_initial: Passed\n",$time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end

0
test_v/t_initial_inc.v → test_regress/t/t_initial_inc.v
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18
test_regress/t/t_math_arith.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

15
test_v/t_arith.v → test_regress/t/t_math_arith.v
View File

@ -4,13 +4,10 @@
// without warranty, 2003 by Wilson Snyder.
module t_arith(/*AUTOARG*/
// Outputs
passed,
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
reg _ranit;
reg [2:0] xor3;
@ -48,7 +45,6 @@ module t_arith(/*AUTOARG*/
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_arith: Running\n",$time);
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
@ -56,9 +52,7 @@ module t_arith(/*AUTOARG*/
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
// surefire lint_off CNDWID
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// surefire lint_on CNDWID
// verilator lint_on WIDTH
// surefire lint_off SEQASS
@ -101,11 +95,6 @@ module t_arith(/*AUTOARG*/
mb = 3'h4;
mc = 10'h5;
// surefire lint_off ASWESB
// surefire lint_off ASWESS
// surefire lint_off ASWEMB
// surefire lint_off CWECBB
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
@ -122,8 +111,8 @@ module t_arith(/*AUTOARG*/
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
$write("[%0t] t_arith: Passed\n",$time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end

18
test_regress/t/t_mem_first.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

8
test_v/t_mem.v → test_regress/t/t_mem_first.v
View File

@ -4,14 +4,11 @@
// without warranty, 2003 by Wilson Snyder.
module t_mem (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
integer _mode; initial _mode = 0;
reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
@ -40,7 +37,6 @@ module t_mem (/*AUTOARG*/
always @ (posedge clk) begin
if (_mode!=0) begin
$write("[%0t] t_mem: Running\n", $time);
wrd0[0] = 32'h1;
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
@ -98,8 +94,8 @@ module t_mem (/*AUTOARG*/
//$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]);
if (vec_wide != {4'b101_1,31'd0}) $stop;
//
$write("[%0t] t_mem: Passed\n", $time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end

18
test_regress/t/t_rnd.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

13
test_v/t_rnd.v → test_regress/t/t_rnd.v
View File

@ -4,23 +4,17 @@
// without warranty, 2003 by Wilson Snyder.
module t_rnd(/*AUTOARG*/
// Outputs
passed,
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
reg _ranit;
reg [2:0] a;
reg [33:0] wide;
// surefire lint_off UDDSCN
reg unused_r;
// surefire lint_on UDDSCN
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin : blockName
@ -36,20 +30,17 @@ module t_rnd(/*AUTOARG*/
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_rnd: Running\n", $time);
//
a = 3'b1xx;
wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000;
$write("[%0t] t_rnd: Value %b %b\n", $time, a, wide[31:0]);
if (one !== 1'b1) $stop;
if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop;
//
$write("[%0t] t_rnd: Passed\n", $time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_off UDDSDN
// verilator lint_off UNUSED
wire _unused_ok = |{1'b1, wide};
// verilator lint_on UNUSED

36
test_v/t.v
View File

@ -21,20 +21,12 @@ module t (/*AUTOARG*/
// verilator lint_on MULTIDRIVEN
wire passed = &passedv;
t_arith tarith
(.passed (passedv[0]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[0] = 1'b1;
assign passedv[1] = 1'b1;
assign passedv[2] = 1'b1;
assign passedv[3] = 1'b1;
assign passedv[4] = 1'b1;
t_initial tinitial
(.passed (passedv[5]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[5] = 1'b1;
t_inst tinst
(.passed (passedv[6]),
/*AUTOINST*/
@ -46,16 +38,8 @@ module t (/*AUTOARG*/
/*AUTOINST*/
// Inputs
.clk (clk));
t_rnd trnd
(.passed (passedv[8]),
/*AUTOINST*/
// Inputs
.clk (clk));
t_mem tmem
(.passed (passedv[9]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[8] = 1'b1;
assign passedv[9] = 1'b1;
assign passedv[10] = 1'b1;
t_clk tclk
(.passed (passedv[11]),
@ -65,11 +49,7 @@ module t (/*AUTOARG*/
.clk (clk),
.reset_l (reset_l));
assign passedv[12] = 1'b1;
t_func tfunc
(.passed (passedv[13]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[13] = 1'b1;
t_chg tchg
(.passed (passedv[14]),
/*AUTOINST*/
@ -80,11 +60,7 @@ module t (/*AUTOARG*/
assign passedv[16] = 1'b1;
assign passedv[17] = 1'b1;
assign passedv[18] = 1'b1;
t_task ttask
(.passed (passedv[19]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[19] = 1'b1;
t_netlist tnetlist
(.passed (passedv[20]),
.also_fastclk (fastclk),

42
test_v/t_func.v
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@ -1,42 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_func (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk
);
// surefire lint_off _NETNM
// surefire lint_off STMINI
input clk;
output passed; reg passed; initial passed = 0;
integer _mode; initial _mode = 0;
wire [2:0] b3; reg [2:0] g3;
wire [5:0] b6; reg [5:0] g6;
t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
always @ (posedge clk) begin
if (_mode==0) begin
_mode <= 1;
$write("[%0t] t_func: Running\n",$time);
g3 <= 3'b101;
g6 <= 6'b110101;
end
else if (_mode==1) begin
if (b3 !== 3'b110) $stop;
if (b6 !== 6'b100110) $stop;
$write("[%0t] t_func: Passed\n",$time);
passed <= 1'b1;
_mode <= 2;
end
end
endmodule