From 2582a833761a078d768aedd2ad3105eaa0b56852 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 13 Mar 2019 19:52:23 -0400
Subject: [PATCH] Unsupported error on select of concatenation

---
 src/V3LinkResolve.cpp                   |  5 +++
 src/verilog.y                           |  7 +++
 test_regress/t/t_math_concat_sel_bad.pl | 17 ++++++++
 test_regress/t/t_math_concat_sel_bad.v  | 58 +++++++++++++++++++++++++
 4 files changed, 87 insertions(+)
 create mode 100755 test_regress/t/t_math_concat_sel_bad.pl
 create mode 100644 test_regress/t/t_math_concat_sel_bad.v

diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 5922ed472..6f94aaf71 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -210,6 +210,11 @@ private:
             } else if (AstEnumItemRef* fromp = VN_CAST(basefromp, EnumItemRef)) {
 		nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::ENUM_BASE,
 					   fromp->cloneTree(false)));
+            } else if (VN_IS(basefromp, Replicate)) {
+                // From {...}[...] syntax in IEEE 2017
+                if (basefromp) { UINFO(1,"    Related node: "<<basefromp<<endl); }
+                nodep->v3error("Unsupported: Select of concatenation");
+		nodep = NULL;
 	    } else {
 		if (basefromp) { UINFO(1,"    Related node: "<<basefromp<<endl); }
 		nodep->v3fatalSrc("Illegal bit select; no signal/member being extracted from");
diff --git a/src/verilog.y b/src/verilog.y
index 6d535c6e4..8e94a5e4e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3295,6 +3295,13 @@ exprOkLvalue<nodep>:		// expression that's also OK to use as a variable_lvalue
 	//			// IEEE: concatenation/constant_concatenation
 	//			// Replicate(1) required as otherwise "{a}" would not be self-determined
 	|	'{' cateList '}'			{ $$ = new AstReplicate($1,$2,1); }
+	|	'{' cateList '}' '[' expr ']'		{ $$ = new AstSelBit($4, new AstReplicate($1,$2,1), $5); }
+	|	'{' cateList '}' '[' constExpr ':' constExpr ']'
+							{ $$ = new AstSelExtract($4, new AstReplicate($1,$2,1), $5, $7); }
+	|	'{' cateList '}' '[' expr yP_PLUSCOLON constExpr ']'
+							{ $$ = new AstSelPlus($4, new AstReplicate($1,$2,1), $5, $7); }
+	|	'{' cateList '}' '[' expr yP_MINUSCOLON constExpr ']'
+							{ $$ = new AstSelMinus($4, new AstReplicate($1,$2,1), $5, $7); }
 	//			// IEEE: assignment_pattern_expression
 	//			// IEEE: [ assignment_pattern_expression_type ] == [ ps_type_id /ps_paremeter_id/data_type]
 	//			// We allow more here than the spec requires
diff --git a/test_regress/t/t_math_concat_sel_bad.pl b/test_regress/t/t_math_concat_sel_bad.pl
new file mode 100755
index 000000000..41002ca7a
--- /dev/null
+++ b/test_regress/t/t_math_concat_sel_bad.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_concat_sel_bad.v b/test_regress/t/t_math_concat_sel_bad.v
new file mode 100644
index 000000000..78ec137eb
--- /dev/null
+++ b/test_regress/t/t_math_concat_sel_bad.v
@@ -0,0 +1,58 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc=0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [3:0]  a = crc[3:0];
+   wire [3:0]  b = crc[19:16];
+
+   // TEST
+   wire [3:0]  out1 = {a,b}[2 +: 4];
+   wire [3:0]  out2 = {a,b}[5 -: 4];
+   wire [3:0]  out3 = {a,b}[5 : 2];
+   wire [0:0]  out4 = {a,b}[2];
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {51'h0, out4, out3, out2, out1};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc<10) begin
+         sum <= '0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h4afe43fb79d7b71e
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule